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型號(hào)：	UPD70F3357GJ(A)-GAE-AX
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, LEAD FREE, PLASTIC, LQFP-144
文件頁(yè)數(shù)：	764/1119頁(yè)
文件大小：	6653K
代理商：	UPD70F3357GJ(A)-GAE-AX

CHAPTER 18 IEBus CONTROLLER

User’s Manual U17790EJ2V0UD

(e) Overrun error occurrence flag (OERR) … Bit 3

This flag is set (1) if an overrun error occurs.

Clear: By software

If 1-byte data is stored in the DR register while the IEBus controller serves as a receiver unit, the data

request interrupt request signal (INTIE1) is generated, and the DR register is read by means of DMA or by

software. If this reading is delayed and the next data is received, an overrun error occurs.

Cautions 1. If the DR register is not read and the number of retransmitted data reaches the

maximum number of transmitted bytes (32 bytes) after the overrun error has occurred,

the frame end interrupt request signal (INTSTA or INTIE2) occurs. The overrun status

is maintained until the DR register is read, even after the frame has ended.

2. The overrun status is cleared only when the DR register is read and when the system

is reset.

Therefore, be sure to read the DR register in the communication error

interrupt processing program.

3. The next data cannot be transmitted in the overrun status if it is 2 bytes or more.

Because the data request interrupt request signal (INTIE1) does not occur, the

transmit data cannot be set and an underrun error occurs.

Therefore, be sure to

execute transmission after clearing the overrun status.

During individual communication reception, the NACK signal is returned during the

acknowledge bit period of the next data. In response, the transmitter unit retransmits data.

Therefore, the CCR register is decremented but the SCR register is not decremented.

During broadcast communication reception, the communication error interrupt request signal

(INTIE2) is generated and reception is stopped. At this time, the DR register is not updated.

The INTIE1 signal is not generated. The STATRX bit of the SSR register is held set (to 1). The

overrun status is cleared when data is received after the DR register has been read.

Figure 18-14. Timing of Overrun Error Occurrence

Request to write data to

Overrun error occurs if data is not

written to DR register during this period.

P: Parity bit

A: Acknowledge bit

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