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型號(hào)：	UPD70F3357GJ(A)-GAE-AX
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, LEAD FREE, PLASTIC, LQFP-144
文件頁(yè)數(shù)：	1011/1119頁(yè)
文件大?。?/td>	6653K
代理商：	UPD70F3357GJ(A)-GAE-AX

CHAPTER 20 DMA FUNCTION (DMA CONTROLLER)

User’s Manual U17790EJ2V0UD

(8) Bus arbitration for CPU

Because the DMA controller has a higher priority bus mastership than the CPU, a CPU access that takes place

during DMA transfer is held pending until the DMA transfer cycle is completed and the bus is released to the

However, the CPU can access the external memory, on-chip peripheral I/O, and internal RAM to/from which

DMA transfer is not being executed.

The CPU can access the internal RAM when DMA transfer is being executed between the external memory

and on-chip peripheral I/O.

The CPU can access the internal RAM and on-chip peripheral I/O when DMA transfer is being executed

between the external memory and external memory.

(9) Registers/bits that must not be rewritten during DMA operation

Set the following registers at the following timing when a DMA operation is not under execution.

DSAnH, DSAnL, DDAnH, DDAnL, DBCn, and DADCn registers

DTFRn.IFCn5 to DTFRn.IFCn0 bits

[Timing of setting]

Period from after reset to start of the first DMA transfer

Time after channel initialization to start of DMA transfer

Period from after completion of DMA transfer (TCn bit = 1) to start of the next DMA transfer

(10) Be sure to set the following register bits to 0.

Bits 14 to 10 of DSAnH register

Bits 14 to 10 of DDAnH register

Bits 15, 13 to 8, and 3 to 0 of DADCn register

Bits 6 to 3 of DCHCn register

(11) DMA start factor

Care must be exercised when setting the same start trigger for multiple DMA channels.

If DMA transfers via such DMA channels are activated, the DMA channel with a lower priority may be

acknowledged prior to the DMA channel with a higher priority.

(12) Read values of DSAn and DDAn registers

Values in the middle of updating may be read from the DSAn and DDAn registers during DMA transfer (n = 0

For example, if the DSAnH register and then the DSAnL register are read when the DMA transfer source

address (DSAn register) is 0000FFFFH and the count direction is incremental (DADCn.SAD1 and

DADCn.SAD0 bits = 00), the value of the DSAn register differs as follows, depending on whether DMA

transfer is executed immediately after the DSAnH register is read.

(a) If DMA transfer does not occur while DSAn register is read

<1> Read value of DSAnH register: DSAnH = 0000H

<2> Read value of DSAnL register: DSAnL = FFFFH

(b) If DMA transfer occurs while DSAn register is read

<1> Read value of DSAnH register: DSAnH = 0000H

<2> Occurrence of DMA transfer

<3> Incrementing DSAn register: DSAn = 00100000H

<4> Read value of DSAnL register: DSAnL = 0000H

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