
APPENDIX D INSTRUCTION SET LIST
User’s Manual U17790EJ2V0UD
1113
(5/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z SAT
bit#3,disp16[reg1]
00bbb111110RRRRR
dddddddddddddddd
adr
←GR[reg1]+sign-extend(disp16)
Z flag
←Not (Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,1)
3
Note3
3
Note3
3
Note3
×
SET1
reg2,[reg1]
r r r r r 1 1 1 1 1 1 R RRR R
0000000011100000
adr
←GR[reg1]
Z flag
←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,1)
3
Note3
3
Note3
3
Note3
×
reg1,reg2
r r r r r 1 1 1 1 1 1 R RRR R
0000000011000000
GR[reg2]
←GR[reg2] logically shift left by GR[reg1]
1
×
0
×
SHL
imm5,reg2
rrrrr01011 0i iiii
GR[reg2]
←GR[reg2] logically shift left
by zero-extend(imm5)
1
×
0
×
reg1,reg2
r r r r r 1 1 1 1 1 1 R RRR R
0000000010000000
GR[reg2]
←GR[reg2] logically shift right by GR[reg1]
1
×
0
×
SHR
imm5,reg2
rrrrr01010 0i iiii
GR[reg2]
←GR[reg2] logically shift right
by zero-extend(imm5)
1
×
0
×
SLD.B
disp7[ep],reg2
r r r r r 0 1 1 0 d d d d d d d
adr
←ep+zero-extend(disp7)
GR[reg2]
←sign-extend(Load-memory(adr,Byte))
1
1 Note9
SLD.BU
disp4[ep],reg2
rrr rr 00 00 11 0d d d d
Note 18
adr
←ep+zero-extend(disp4)
GR[reg2]
←zero-extend(Load-memory(adr,Byte))
1
1 Note9
SLD.H
disp8[ep],reg2
r r r r r 1 0 0 0 d d d d d d d
Note 19
adr
←ep+zero-extend(disp8)
GR[reg2]
←sign-extend(Load-memory(adr,Halfword))
1
1 Note9
SLD.HU
disp5[ep],reg2
rrrrr000 0111d ddd
Notes 18, 20
adr
←ep+zero-extend(disp5)
GR[reg2]
←zero-extend(Load-memory(adr,Halfword))
1
1 Note9
SLD.W
disp8[ep],reg2
rrrrr101 0dddd dd0
Note 21
adr
←ep+zero-extend(disp8)
GR[reg2]
←Load-memory(adr,Word)
1
1 Note9
SST.B
reg2,disp7[ep]
r r r r r 0 1 1 1 d d d d d d d
adr
←ep+zero-extend(disp7)
Store-memory(adr,GR[reg2],Byte)
1
SST.H
reg2,disp8[ep]
r r r r r 1 0 0 1 d d d d d d d
Note 19
adr
←ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Halfword)
1
SST.W
reg2,disp8[ep]
rrrrr101 0dddd dd1
Note 21
adr
←ep+zero-extend(disp8)
Store-memory(adr,GR[reg2],Word)
1
ST.B
reg2,disp16[reg1]
r r r r r 1 1 1 0 1 0 R RRR R
dddddddddddddddd
adr
←GR[reg1]+sign-extend(disp16)
Store-memory(adr,GR[reg2],Byte)
1
ST.H
reg2,disp16[reg1]
r r r r r 1 1 1 0 1 1 R RRR R
ddddddddddddddd0
Note 8
adr
←GR[reg1]+sign-extend(disp16)
Store-memory (adr,GR[reg2], Halfword)
1
ST.W
reg2,disp16[reg1]
rrrrr111011RRRRR
ddddddddddddddd1
Note 8
adr
←GR[reg1]+sign-extend(disp16)
Store-memory (adr,GR[reg2], Word)
1
STSR
regID,reg2
r r r r r 1 1 1 1 1 1 R RRR R
0000000001000000
GR[reg2]
←SR[regID]
1