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型號(hào)：	UPD70F3357GJ(A)-GAE-AX
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, LEAD FREE, PLASTIC, LQFP-144
文件頁(yè)數(shù)：	704/1119頁(yè)
文件大?。?/td>	6653K
代理商：	UPD70F3357GJ(A)-GAE-AX

CHAPTER 17 I

User’s Manual U17790EJ2V0UD

17.9 Address Match Detection Method

2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave

Address match detection is performed automatically by hardware. The INTIICn signal occurs when a local address

has been set to the SVAn register and when the address set to the SVAn register matches the slave address sent by

the master device, or when an extension code has been received (n = 0 to 2).

17.10 Error Detection

2C bus mode, the status of the serial data bus pin (SDA0n) during data transmission is captured by the IICn

transmitted IICn data to enable detection of transmission errors. A transmission error is judged as having occurred

when the compared data values do not match (n = 0 to 2).

17.11 Extension Code

(1) When the higher 4 bits of the receive address are either 0000 or 1111, the extension code flag (IICSn.EXCn

bit) is set for extension code reception and an interrupt request signal (INTIICn) is issued at the falling edge of

the eighth clock (n = 0 to 2).

The local address stored in the SVAn register is not affected.

(2) If 11110xx0 is set to the SVAn register by a 10-bit address transfer and 11110xx0 is transferred from the

master device, the results are as follows. Note that the INTIICn signal occurs at the falling edge of the eighth

clock (n = 0 to 2).

Higher four bits of data match: EXCn bit = 1

Seven bits of data match:

IICSn.COIn bit = 1

(3) Since the processing after the interrupt request signal occurs differs according to the data that follows the

extension code, such processing is performed by software.

For example, when operation as a slave is not desired after the extension code is received, set the

IICCn.LRELn bit to 1 and the CPU will enter the next communication wait state.

Table 17-4. Extension Code Bit Definitions

Slave Address

General call address

CBUS address

Address that is reserved for different bus format

10-bit slave address specification

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