
APPENDIX D INSTRUCTION SET LIST
User’s Manual U17790EJ2V0UD
1111
(3/6)
Execution
Clock
Flags
Mnemonic
Operand
Opcode
Operation
i
r
l
CY OV
S
Z SAT
LD.H
disp16[reg1],reg2
rrrrr111001RRRRR
ddddddddddddddd0
Note 8
adr
←GR[reg1]+sign-extend(disp16)
GR[reg2]
←sign-extend(Load-memory(adr,Halfword))
1
Note
11
Other than regID = PSW
1
LDSR
reg2,regID
rrrrr111111RRRRR
0000000000100000
Note 12
SR[regID]
←GR[reg2]
regID = PSW
1
×
LD.HU
disp16[reg1],reg2
r r r r r 1 1 1 1 1 1 R RRR R
ddddddddddddddd1
Note 8
adr
←GR[reg1]+sign-extend(disp16)
GR[reg2]
←zero-extend(Load-memory(adr,Halfword)
1
Note
11
LD.W
disp16[reg1],reg2
r r r r r 1 1 1 0 0 1 R RRR R
ddddddddddddddd1
Note 8
adr
←GR[reg1]+sign-extend(disp16)
GR[reg2]
←Load-memory(adr,Word)
1
Note
11
reg1,reg2
r r r r r 0 0 0 0 0 0 R RRR R
GR[reg2]
←GR[reg1]
1
imm5,reg2
r r r r r 0 1 0 000i i iii
GR[reg2]
←sign-extend(imm5)
1
MOV
imm32,reg1
00000110001RRRRR
iiiiiiiiiiiii iii
IIIIII IIII III III
GR[reg1]
←imm32
2
MOVEA
imm16,reg1,reg2
r r r r r 1 1 0 0 0 1 R RRR R
iii ii iii ii ii i iii
GR[reg2]
←GR[reg1]+sign-extend(imm16)
1
MOVHI
imm16,reg1,reg2
r r r r r 1 1 0 0 1 0 R RRR R
iii ii iii ii ii i iii
GR[reg2]
←GR[reg1]+(imm16 ll 016)
1
reg1,reg2,reg3
r r r r r 1 1 1 1 1 1 R RRR R
wwwww01000100000
GR[reg3] ll GR[reg2]
←GR[reg2]xGR[reg1]
Note 14
1
4
5
MUL
imm9,reg2,reg3
rrrrr11111 1i iiii
wwwww01001IIII 00
Note 13
GR[reg3] ll GR[reg2]
←GR[reg2]xsign-extend(imm9)
1
4
5
reg1,reg2
r r r r r 0 0 0 1 1 1 R RRR R
GR[reg2]
←GR[reg2]Note 6xGR[reg1]Note 6
1
2
MULH
imm5,reg2
r r r r r 0 1 0 111i i iii
GR[reg2]
←GR[reg2]Note 6xsign-extend(imm5)
1
2
MULHI
imm16,reg1,reg2
r r r r r 1 1 0 1 1 1 R RRR R
iii ii iii ii ii i iii
GR[reg2]
←GR[reg1]Note 6ximm16
1
2
reg1,reg2,reg3
r r r r r 1 1 1 1 1 1 R RRR R
wwwww01000100010
GR[reg3] ll GR[reg2]
←GR[reg2]xGR[reg1]
Note 14
1
4
5
MULU
imm9,reg2,reg3
rrrrr11111 1i iiii
wwwww01001IIII 10
Note 13
GR[reg3] ll GR[reg2]
←GR[reg2]xzero-extend(imm9)
1
4
5
NOP
0000000000000000
Pass at least one clock cycle doing nothing.
1
NOT
reg1,reg2
r r r r r 0 0 0 0 0 1 R RRR R
GR[reg2]
←NOT(GR[reg1])
1
0
×
bit#3,disp16[reg1]
01bbb111110RRRRR
dddddddddddddddd
adr
←GR[reg1]+sign-extend(disp16)
Z flag
←Not(Load-memory-bit(adr,bit#3))
Store-memory-bit(adr,bit#3,Z flag)
3
Note3
3
Note3
3
Note3
×
NOT1
reg2,[reg1]
r r r r r 1 1 1 1 1 1 R RRR R
0000000011100010
adr
←GR[reg1]
Z flag
←Not(Load-memory-bit(adr,reg2))
Store-memory-bit(adr,reg2,Z flag)
3
Note3
3
Note3
3
Note3
×