
CHAPTER 17 I
2C BUS
User’s Manual U17790EJ2V0UD
589
Table 17-2. Clock Settings (2/2)
IICXm
IICCLm
Bit 0
Bit 3
Bit 1
Bit 0
CLXm SMCm CLm1
CLm0
Selection Clock
Transfer
Clock
Settable Main Clock
Frequency (fXX) Range
Operating
Mode
fXX (when OCKS1 = 18H set)
fXX/44
2.00 MHz
≤ fXX ≤ 4.19 MHz
fXX/2 (when OCKS1 = 10H set)
fXX/88
4.00 MHz
≤ fXX ≤ 8.38 MHz
fXX/3 (when OCKS1 = 11H set)
fXX/132
6.00 MHz
≤ fXX ≤ 12.57 MHz
fXX/4 (when OCKS1 = 12H set)
fXX/176
8.00 MHz
≤ fXX ≤ 16.76 MHz
0
fXX/5 (when OCKS1 = 13H set)
fXX/220
10.00 MHz
≤ fXX ≤ 20.95 MHz
fXX (when OCKS1 = 18H set)
fXX/86
4.19 MHz
≤ fXX ≤ 8.38 MHz
fXX/2 (when OCKS1 = 10H set)
fXX/172
8.38 MHz
≤ fXX ≤ 16.76 MHz
fXX/3 (when OCKS1 = 11H set)
fXX/258
12.57 MHz
≤ fXX ≤ 25.14 MHz
fXX/4 (when OCKS1 = 12H set)
fXX/344
16.76 MHz
≤ fXX ≤ 32.00 MHz
0
1
fXX/5 (when OCKS1 = 13H set)
fXX/430
20.95 MHz
≤ fXX ≤ 32.00 MHz
0
1
0
fXX
Note
fXX/86
4.19 MHz
≤ fXX ≤ 8.38 MHz
fXX (when OCKS1 = 18H set)
fXX/66
6.40 MHz
fXX/2 (when OCKS1 = 10H set)
fXX/132
12.80 MHz
fXX/3 (when OCKS1 = 11H set)
fXX/198
19.20 MHz
fXX/4 (when OCKS1 = 12H set)
fXX/264
25.60 MHz
0
1
fXX/5 (when OCKS1 = 13H set)
fXX/330
32.00 MHz
Standard
mode
(SMCm bit = 0)
fXX (when OCKS1 = 18H set)
fXX/24
4.19 MHz
≤ fXX ≤ 8.38 MHz
fXX/2 (when OCKS1 = 10H set)
fXX/48
8.00 MHz
≤ fXX ≤ 16.76 MHz
fXX/3 (when OCKS1 = 11H set)
fXX/72
12.00 MHz
≤ fXX ≤ 25.14 MHz
0
1
0
×
fXX/4 (when OCKS1 = 12H set)
fXX/96
16.00 MHz
≤ fXX ≤ 32.00 MHz
0
1
0
fXX
Note
fXX/24
4.00 MHz
≤ fXX ≤ 8.38 MHz
fXX (when OCKS1 = 18H set)
fXX/18
6.40 MHz
fXX/2 (when OCKS1 = 10H set)
fXX/36
12.80 MHz
fXX/3 (when OCKS1 = 11H set)
fXX/54
19.20 MHz
fXX/4 (when OCKS1 = 12H set)
fXX/72
25.60 MHz
0
1
fXX/5 (when OCKS1 = 13H set)
fXX/90
32.00 MHz
fXX (when OCKS1 = 18H set)
fXX/12
4.00 MHz
≤ fXX ≤ 4.19 MHz
fXX/2 (when OCKS1 = 10H set)
fXX/24
8.00 MHz
≤ fXX ≤ 8.38 MHz
fXX/3 (when OCKS1 = 11H set)
fXX/36
12.00 MHz
≤ fXX ≤ 12.57 MHz
fXX/4 (when OCKS1 = 12H set)
fXX/48
16.00 MHz
≤ fXX ≤ 16.67 MHz
1
0
×
fXX/5 (when OCKS1 = 13H set)
fXX/60
20.00 MHz
≤ fXX ≤ 20.95 MHz
1
0
fXX
Note
fXX/12
4.00 MHz
≤ fXX ≤ 4.19 MHz
High-speed
mode
(SMCm bit = 1)
Other than above
Setting prohibited
Note
Since the selection clock is fXX regardless of the value set to the OCKS1 register, clear the OCKS1 register
to 00H (I
2C division clock stopped status).
Remarks 1.
m = 1, 2
2.
×: don’t care