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型號：	UPD70F3357GJ(A)-GAE-AX
元件分類：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, LEAD FREE, PLASTIC, LQFP-144
文件頁數(shù)：	749/1119頁
文件大?。?/td>	6653K
代理商：	UPD70F3357GJ(A)-GAE-AX

CHAPTER 18 IEBus CONTROLLER

User’s Manual U17790EJ2V0UD

(a) Communication enable flag (ENIEBUS)...Bit 7

Clear: By software

The IEBus controller participates in communication differently depending on the timing of setting the

ENIEBUS bit (1), as follows.

Table 18-10. Timing of Setting ENIEBUS Bit and Participation in Communication

Timing of Setting ENIEBUS Bit

How IEBus Controller Participates in Communication

If communication is not performed on IEBus

Participates in communication from the next frame or starts

communication.

If other bus master is communicating start bit

while communication is in progress on IEBus

Participates in communication from that frame if the start bit is

detected. If the start bit is not detected, participates in

communication from the next frame.

If communication is in progress on IEBus after

start bit from other bus master is detected

Participates in communication from the next frame.

If the ENIEBUS bit is cleared (0), communication is immediately stopped even while it is in progress, and

the internal flags and registers are reset, with some exceptions. The registers that are not reset by the

ENIEBUS bit are listed in the table below.

The IEBus controller does not respond even if another unit starts communication when the ENIEBUS bit =

Table 18-11. Registers That Are Not Reset by ENIEBUS Bit

Registers Not Reset by ENIEBUS Bit

Data written from CPU is not reset but data received during

communication is reset.

Data written from CPU is not reset but data received during

communication is reset.

Data written from CPU is not reset but data received during

communication is reset.

Before setting the ENIEBUS bit (1), the following registers must be set depending on the mode

of communication to be started.

Table 18-12. Registers That Must Be Set Before Each Communication

Mode of Communication

Registers That Must Be Set in Advance

Master transmission

UAR, SAR, CDR, DLR, DR (first 1-byte data)

Master reception

UAR, SAR, CDR

Slave transmission

UAR, DLR, DR (first 1-byte data)

Slave reception

Note When starting slave transmission, information such as the value to be set to the DLR register and which

data is to be returned (value to be set to the DR register) must be assigned in advance.

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