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型號(hào)：	UPD70F3357GJ(A)-GAE-AX
元件分類(lèi)：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, LEAD FREE, PLASTIC, LQFP-144
文件頁(yè)數(shù)：	713/1119頁(yè)
文件大?。?/td>	6653K
代理商：	UPD70F3357GJ(A)-GAE-AX

CHAPTER 17 I

User’s Manual U17790EJ2V0UD

17.15 Cautions

(1) When IICFn.STCENn bit = 0

Immediately after the I

2C0n operation is enabled, the bus communication status (IICFn.IICBSYn bit = 1) is

recognized regardless of the actual bus status. To execute master communication in the status where a stop

condition has not been detected, generate a stop condition and then release the bus before starting the master

communication.

Use the following sequence for generating a stop condition.

<1> Set the IICCLn register.

<2> Set the IICCn.IICEn bit.

<3> Set the IICCn.SPTn bit.

(2) When IICFn.STCENn bit = 1

Immediately after I

2C0n operation is enabled, the bus released status (IICBSYn bit = 0) is recognized

regardless of the actual bus status. To generate the first start condition (IICCn.STTn bit = 1), it is necessary to

confirm that the bus has been released, so as to not disturb other communications.

(3) When the IICCn.IICEn bit of the V850ES/SJ3 is set to 1 while communications with other devices are in

progress, the start condition may be detected depending on the status of the communication line. Be sure to

set the IICCn.IICEn bit to 1 when the SCL0n and SDA0n lines are high level.

(4) Determine the operation clock frequency by the IICCLn, IICXn, and OCKSm registers before enabling the

operation (IICCn.IICEn bit = 1). To change the operation clock frequency, clear the IICCn.IICEn bit to 0 once.

(5) After the IICCn.STTn and IICCn.SPTn bits have been set to 1, they must not be re-set without being cleared to

(6) If transmission has been reserved, set the IICCN.SPIEn bit to 1 so that an interrupt request is generated by the

detection of a stop condition. After an interrupt request has been generated, the wait state will be released by

writing communication data to I

2Cn, then transferring will begin. If an interrupt is not generated by the detection

of a stop condition, transmission will halt in the wait state because an interrupt request was not generated.

However, it is not necessary to set the SPIEn bit to 1 for the software to detect the IICSn.MSTSn bit.

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