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型號(hào)：	UPD70F3357GJ(A)-GAE-AX
元件分類(lèi)：	微控制器/微處理器
英文描述：	32-BIT, FLASH, 32 MHz, RISC MICROCONTROLLER, PQFP144
封裝：	20 X 20 MM, LEAD FREE, PLASTIC, LQFP-144
文件頁(yè)數(shù)：	1073/1119頁(yè)
文件大?。?/td>	6653K
代理商：	UPD70F3357GJ(A)-GAE-AX

CHAPTER 24 STANDBY FUNCTION

User’s Manual U17790EJ2V0UD

24.5 IDLE2 Mode

24.5.1 Setting and operation status

The IDLE2 mode is set by setting the PSMR.PSM1 and PSMR.PSM0 bits to 10 and setting the PSC.STP bit to 1 in

the normal operation mode.

In the IDLE2 mode, the clock oscillator continues operation but clock supply to the CPU, PLL, flash memory, and

other on-chip peripheral functions stops.

As a result, program execution stops and the contents of the internal RAM before the IDLE2 mode was set are

retained. The CPU, PLL, and other on-chip peripheral functions stop operating. However, the on-chip peripheral

functions that can operate with the subclock or an external clock continue operating.

Table 24-7 shows the operating status in the IDLE2 mode.

The IDLE2 mode can reduce the power consumption more than the IDLE1 mode because it stops the operations of

the on-chip peripheral functions, PLL, and flash memory. However, because the PLL and flash memory are stopped,

a setup time for the PLL and flash memory is required when IDLE2 mode is released.

Cautions 1. Insert five or more NOP instructions after the instruction that stores data in the PSC register

to set the IDLE2 mode.

2. If the IDLE2 mode is set while an unmasked interrupt request signal is being held pending,

the IDLE2 mode is released immediately by the pending interrupt request.

24.5.2 Releasing IDLE2 mode

The IDLE2 mode is released by a non-maskable interrupt request signal (NMI pin input, INTWDT2 signal),

unmasked external interrupt request signal (INTP0 to INTP8 pin input), unmasked internal interrupt request signal

from the peripheral functions operable in the IDLE2 mode, or reset signal (reset by RESET pin input, WDT2RES

signal, low-voltage detector (LVI), or clock monitor (CLM)). The PLL returns to the operating status it was in before

the IDLE2 mode was set.

After the IDLE2 mode has been released, the normal operation mode is restored.

(1) Releasing IDLE2 mode by non-maskable interrupt request signal or unmasked maskable interrupt

request signal

The IDLE2 mode is released by a non-maskable interrupt request signal or an unmasked maskable interrupt

request signal, regardless of the priority of the interrupt request signal. If the IDLE2 mode is set in an interrupt

servicing routine, however, an interrupt request signal that is issued later is processed as follows.

(a) If an interrupt request signal with a priority lower than that of the interrupt request currently being serviced

is issued, the IDLE2 mode is released, but that interrupt request signal is not acknowledged.

interrupt request signal itself is retained.

(b) If an interrupt request signal with a priority higher than that of the interrupt request currently being

serviced is issued (including a non-maskable interrupt request signal), the IDLE2 mode is released and

that interrupt request signal is acknowledged.

The interrupt request signal that is disabled by setting the PSC.NMI1M, PSC.NMI0M, and

PSC.INTM bits to 1 becomes invalid and IDLE2 mode is not released.

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