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SYM53C876/876E Data Manual
4-3
Registers
PCI Configuration Registers
Register 04h
Command
Read/Write
The SCSI Command Register provides coarse
control over a device’s ability to generate and
respond to PCI cycles. When a zero is written to
this register, the SYM53C876 is logically discon-
nected from the PCI bus for all accesses except
configuration accesses.
Bits 15-9 Reserved
Bit 8
SERR/ Enable(SE)
This bit enables the SERR/ driver. SERR/ is
disabled when this bit is clear. The default
value of this bit is zero. Set this bit and bit 6 to
report address parity errors. In
SYM53C876E, this bit is suppressed in Power
State D2.
Bit 7
Reserved
Bit 6
Enable Parity Error Response
(EPER)
This bit allows a SCSI function of the
SYM53C876E to detect parity errors on the
PCI bus and report these errors to the system.
Only data parity checking is enabled and dis-
abled with this bit. The SYM53C876 always
generates parity for the PCI bus. In
SYM53C876E, this bit is suppressed in Power
State D2.
Bit 5
Reserved
Bit 4
Write and Invalidate Enable (WIE)
This bit allows a SCSI function of the
SYM53C876 to generate write and invalidate
commands on the PCI bus. Set the WRIE bit
in the CTEST3 register also for the SCSI
function to generate write and invalidate com-
mands.
Bit 3
Reserved
Bit 2
Enable Bus Mastering (EBM)
This bit controls the ability of a SCSI function
to act as a master on the PCI bus. A value of
zero disables this device from generating PCI
bus master accesses. A value of one allows the
SCSI function to behave as a bus master.
When the SCSI function is a bus master it can
fetch SCRIPTS instructions and transfer data.
In SYM53C876E, this bit is suppressed in
Power State D2.
Bit 1
Enable Memory Space (EMS)
This bit controls the ability of a SCSI function
to respond to Memory space accesses. A value
of zero disables the device response. A value
of one allows a SCSI function of the
SYM53C876 to respond to Memory Space
accesses at the address range specified by the
Base Address One and Base Address Two reg-
isters in the SCSI function’s PCI configura-
tion space. In SYM53C876E, this bit is
suppressed in Power State D2.
Bit 0
Enable I/O Space (EIS)
This bit controls a SCSI function’s response
to I/O space accesses. A value of zero disables
the device response. A value of one allows a
SCSI function to respond to I/O Space
accesses at the address range specified by the
Base Address Zero register in the SCSI func-
tion’s PCI configuration space. In
SYM53C876E, this bit is suppressed in Power
State D2.
RES
15-9
Default >>>
0
SE
8
RES
7
EPER
6
RES
5
WIE
4
RES
3
EBM
2
EMS
1
EIS
0
0
0
0
0
0
0
0
0
0