參數(shù)資料
型號(hào)： SYM53C876
廠商： LSI Corporation
英文描述： PCI-Dual Channel SCSI Multi-Function Controller(PCI 雙通道SCSI多功能控制器)
中文描述： 的PCI -雙通道SCSI多功能控制器（雙通道的PCI的SCSI多功能控制器）
文件頁(yè)數(shù)： 59/285頁(yè)
文件大?。?/td> 3341K
代理商： SYM53C876
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SYM53C876/876E Data Manual
2-25
Functional Description
SCSI Functional Description
dition occurs, SCRIPTS halts and the system
never knows it unless it times out and checks
the ISTAT after a certain period of inactivity.
If you are polling the ISTAT instead of using
hardware interrupts, then masking a fatal
interrupt makes no difference since the SIP
and DIP bits in the ISTAT inform the system
of interrupts, not the INTA/ (or INTB/) pin.
Masking an interrupt after INTA/ (or INTB/)
is asserted does not cause deassertion of
INTA/ (or INTB/).
Stacked Interrupts
The SYM53C876 stacks interrupts if they
occur one after the other. If the SIP or DIP
bits in the ISTAT register are set (first level),
then there is already at least one pending
interrupt, and any future interrupts are
stacked in extra registers behind the SIST0,
SIST1, and DSTAT registers (second level).
When two interrupts have occurred and the
two levels of the stack are full, any further
interrupts sets additional bits in the extra reg-
isters behind SIST0, SIST1, and DSTAT.
When the first level of interrupts are cleared,
all the interrupts that came in afterward
moves into the SIST0, SIST1, and DSTAT.
After the first interrupt is cleared by reading
the appropriate register, the INTA/ (or INTB/
) pin deasserts for a minimum of three CLKs;
the stacked interrupts move into the SIST0,
SIST1, or DSTAT; and the INTA/ (or INTB/
) pin asserts once again.
Since a masked non-fatal interrupt does not
set the SIP or DIP bits, interrupt stacking
does not occur. A masked, non-fatal interrupt
still posts the interrupt in SIST0, but does not
assert the INTA/ (or INTB/) pin. Since no
interrupt is generated, future interrupts move
right into the SIST0 or SIST1 instead of
being stacked behind another interrupt. When
another condition occurs that generates an
interrupt, the bit corresponding to the earlier
masked non-fatal interrupt is still set.
A related situation to interrupt stacking is
when two interrupts occur simultaneously.
Since stacking does not occur until the SIP or
DIP bits are set, there is a small timing win-
dow in which multiple interrupts can occur
but are not stacked. These could be multiple
SCSI interrupts (SIP set), multiple DMA
interrupts (DIP set), or multiple SCSI and
multiple DMA interrupts (both SIP and DIP
set).
As previously mentioned, DMA interrupts do
not attempt to flush the FIFOs before gener-
ating the interrupt. It is important to set either
the Clear DMA FIFO (CLF) and Clear SCSI
FIFO (CSF) bits if a DMA interrupt occurs,
and the DMA FIFO Empty (DFE) bit is not
set because any future SCSI interrupts are not
posted until the DMA FIFO is clear of data.
These “l(fā)ocked out” SCSI interrupts are
posted as soon as the DMA FIFO is empty.
Halting in an
Orderly Fashion
When an interrupt occurs, the SYM53C876
attempts to halt in an orderly fashion.
n
If the interrupt occurs in the middle of an
instruction fetch, the fetch is completed,
except in the case of a Bus Fault.
Execution does not begin, but the DSP
points to the next instruction since it is
updated when the current instruction is
fetched.
n
If the DMA direction is a write to memory
and a SCSI interrupt occurs, the
SYM53C876 attempts to flush the DMA
FIFO to memory before halting. Under
any other circumstances only the current
cycle is completed before halting, so the
DFE bit in DSTAT should be checked to
see if any data remains in the DMA FIFO.
n
SCSI SREQ/SACK handshakes that have
begun are completed before halting.
n
The SYM53C876 attempts to clean up
any outstanding synchronous offset before
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