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SYM53C876/876E Data Manual
4-25
Registers
SCSI Registers
codes. The value in this bit is reloaded at the
beginning of all asynchronous target receives.
Bit 1
VUE1 (Vendor Unique Enhance-
ment bit 1)
This bit disables the automatic byte count
reload during Block Move instructions in the
command phase. If this bit is reset, the device
reloads the Block Move byte count if the first
byte received is one of the standard group
codes. If this bit is set, the device does not
reload the Block Move byte count, regardless
of the group code.
Bit 0
WSR (Wide SCSI Receive)
When read, this bit returns the value of the
Wide SCSI Receive (WSR) flag. Setting this
bit clears the WSR flag. This clearing function
is self-resetting.
The WSR flag indicates that the SCSI core
received data from the SCSI bus, detected a
possible partial transfer at the end of a
chained or non-chained block move com-
mand, and temporarily stored the high-order
byte in the SWIDE register rather than pass-
ing the byte out the DMA channel. The hard-
ware uses the WSR status flag to determine
what behavior must occur at the start of the
next data receive transfer. When the flag is set,
the stored data in SWIDE may be “residue”
data, valid data for a subsequent data transfer,
or overrun data. The byte is read as normal
data by starting a data receive transfer.
Performing a SCSI send operation clears this
bit. Also, performing any non-wide transfer
clears this bit.
Register 03h
SCSI Control Three (SCNTL3)
Read/Write
Bit 7
USE (Ultra SCSI Enable)
Setting this bit enables Ultra SCSI synchro-
nous transfers. The default value of this bit is
0. Set this bit only when the transfer rate
exceeds 10 Mega-transfers/sec.
When this bit is set, the signal filtering period
for SREQ/ and SACK/ automatically changes
to 15 ns, regardless of the value of the Extend
REQ/ACK Filtering bit in the STEST2 regis-
ter.
Bits 6-4 SCF2-0 (Synchronous Clock
Conversion Factor)
These bits select a factor by which the fre-
quency of SCLK is divided before being pre-
sented to the synchronous SCSI control logic.
Write these to the same value as the Clock
Conversion Factor bits below unless fast SCSI
operation is desired. See the SCSI Transfer
(SXFER) register description for examples of
how the SCF bits are used to calculate syn-
chronous transfer periods. See the table under
the description of bits 7-5 of the SXFER reg-
ister for the valid combinations.
Note: For additional information on how the
synchronous transfer rate is determined,
refer to Chapter 2,
Functional Description
.
USE
7
Default >>>
0
SCF2
6
SCF1
5
SCF0
4
EWS
3
CCF2
2
CCF1
1
CCF0
0
0
0
0
0
0
0
0