
4-52
SYM53C876/876E Data Manual
Registers
SCSI Registers
Bit 3
INTM (INTA Mode)
When set, this bit enables a totem pole driver
for the INTA/, or INTB/ pin. When reset, this
bit enables an open drain driver for the INTA/
, or INTB/, pin with an internal weak pull-up.
This bit is reset at power up. The bit should
remain clear to retain full PCI compliance.
Bit 2
STD (Start DMA Operation)
The SYM53C876 SCSI function fetches a
SCSI SCRIPTS instruction from the address
contained in the DSP register when this bit is
set. This bit is required if the SYM53C876
SCSI function is in one of the following
modes:
1. Manual start mode – Bit 0 in the DMODE
register is set
2. Single-step mode – Bit 4 in the DCNTL
register is set
When the SYM53C876 SCSI function is exe-
cuting SCRIPTS in manual start mode, the
Start DMA bit must be set to start instruction
fetches, but need not be set again until an
interrupt occurs. When the SYM53C876
SCSI function is in single-step mode, set the
Start DMA bit to restart execution of
SCRIPTS after a single-step interrupt.
Bit 1
IRQD (INTA, INTB Disable)
Setting this bit disables the INTA (for SCSI
Function A), or INTB (for SCSI Function B)
pin. Clearing the bit enables normal opera-
tion. As with any other register other than
ISTAT, this register cannot be accessed except
by a SCRIPTS instruction during SCRIPTS
execution. For more information on the use of
this bit in interrupt handling, see Chapter 2.
Bit 0
COM (53C700 Compatibility)
When the COM bit is clear, the SYM53C876
SCSI function behaves in a manner compati-
ble with the SYM53C700; selection/reselec-
tion IDs are stored in both the SSID and
SFBR registers. This bit is not effected by a
software reset.
If the COM bit is cleared, do not access this
register via SCRIPTS operation as non-deter-
minate operations may occur. (This includes
SCRIPTS Read/Write operations and condi-
tional transfer control instructions that initial-
ize the SFBR register.)
When the COM bit is set, the ID is stored
only in the SSID register, protecting the
SFBR from being overwritten if a selection/
reselection occurs during a DMA register-to-
register operation.