
SYM53C876/876E Data Manual
4-63
Registers
SCSI Registers
Register 4Bh
Response ID One (RESPID1)
Read/Write
RESPID0 and RESPID1 contain the selection or
reselection IDs. In other words, these two 8-bit
registers contain the ID that the chip responds to
on the SCSI bus. Each bit represents one possible
ID with the most significant bit of RESPID1 rep-
resenting ID 15 and the least significant bit of
RESPID0 representing ID 0. The SCID register
still contains the chip ID used during arbitration.
The chip can respond to more than one ID
because more than one bit can be set in the
RESPID1 and RESPID0 registers. However, the
chip can arbitrate with only one ID value in the
SCID register.
Register 4Ch
SCSI Test Zero (STEST0)
Read Only
Bits 7-4 SSAID3-0 (SCSI Selected As ID)
These bits contain the encoded value of the
SCSI ID that the SYM53C876 SCSI function
is selected or reselected as during a SCSI
selection or reselection phase. These bits are
read only and contain the encoded value of 0-
15 possible IDs that could be used to select
the SYM53C876 SCSI function. During a
SCSI selection or reselection phase when a
valid ID is put on the bus, and the
SYM53C876 SCSI function responds to that
ID, the “selected as” ID is written into these
bits. These bits are used with the RESPID
registers to allow response to multiple IDs on
the bus.
Bit 3
SLT (Selection Response Logic Test)
This bit is set when the SYM53C876 SCSI
function is ready to be selected or reselected.
This does not take into account the bus settle
delay of 400 ns. This bit is used for functional
test and fault purposes.
Bit 2
ART (Arbitration Priority Encoder
Test)
This bit is always set when the SYM53C876
SCSI function exhibits the highest priority ID
asserted on the SCSI bus during arbitration.
It is primarily used for chip level testing, but it
may be used during low level mode operation
to determine if the SYM53C876 SCSI func-
tion won arbitration.
ID
15
ID
14
ID
13
ID
12
ID
11
ID
10
ID
9
ID
8
Default >>>
X
X
X
X
X
X
X
X
SSAID3 SSAID2 SSAID1 SSAID0
7
6
Default >>>
0
0
SLT
3
ART
2
SOZ
1
SOM
0
5
4
0
0
0
X
1
1