參數(shù)資料
型號(hào)： SYM53C876
廠商： LSI Corporation
英文描述： PCI-Dual Channel SCSI Multi-Function Controller(PCI 雙通道SCSI多功能控制器)
中文描述： 的PCI -雙通道SCSI多功能控制器（雙通道的PCI的SCSI多功能控制器）
文件頁(yè)數(shù)： 172/285頁(yè)
文件大?。?/td> 3341K
代理商： SYM53C876
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5-10
SYM53C876/876E Data Manual
SCSI SCRIPTS Instruction Set
I/O Instructions
that requires a response from the target is
encountered.
3. If the SYM53C876 is selected or reselected
before winning arbitration, it fetches the next
instruction from the address pointed to by the
32-bit jump address field stored in the DNAD
register. Manually set the SYM53C876 to
initiator mode if it is reselected, or to target
mode if it is selected.
4. If the Select with SATN/ field is set, the
SATN/ signal is asserted during the selection
phase.
Wait Disconnect Instruction
The SYM53C876 waits for the target to perform
a “l(fā)egal” disconnect from the SCSI bus. A “l(fā)egal”
disconnect occurs when SBSY/ and SSEL/ are
inactive for a minimum of one Bus Free delay
(400 ns), after the SYM53C876 receives a Dis-
connect Message or a Command Complete Mes-
sage.
Wait Reselect Instruction
1. If the SYM53C876 is selected before being
reselected, it fetches the next instruction from
the address pointed to by the 32-bit jump
address field stored in the DNAD register.
Manually set the SYM53C876 to target mode
when it is selected.
2. If the SYM53C876 is reselected, it fetches the
next instruction from the address pointed to
by the DSP register.
3. If the CPU sets the SIGP bit in the ISTAT
register, the SYM53C876 aborts the Wait
Reselect instruction and fetches the next
instruction from the address pointed to by the
32-bit jump address field stored in the DNAD
register.
Set Instruction
When the SACK/ or SATN/ bits are set, the cor-
responding bits in the SOCL register are set.
When the target bit is set, the corresponding bit in
the SCNTL0 register is also set. When the carry
bit is set, the corresponding bit in the ALU is set.
Clear Instruction
When the SACK/or SATN/ bits are set, the corre-
sponding bits are cleared in the SOCL register.
When the target bit is set, the corresponding bit in
the SCNTL0 register is cleared. When the carry
bit is set, the corresponding bit in the ALU is
cleared.
Bit 26 Relative Addressing Mode
When this bit is set, the 24-bit signed value in
the DNAD register is used as a relative dis-
placement from the current DSP address. Use
this bit only in conjunction with the Select,
Reselect, Wait Select, and Wait Reselect
instructions. The Select and Reselect instruc-
tions can contain an absolute alternate jump
address or a relative transfer address.
Bit 25
Table Indirect Mode
When this bit is set, the 24-bit signed value in
the DBC register is added to the value in the
DSA register, used as an offset relative to the
value in the Data Structure Base Address
(DSA) register. The SCNTL3 value, SCSI
ID, synchronous offset and synchronous
period are loaded from this address. Prior to
the start of an I/O, load the DSA with the base
address of the I/O data structure. Any address
on a longword boundary is allowed. After a
Table Indirect op code is fetched, the DSA is
added to the 24-bit signed offset value from
the op code to generate the address of the
required data. Both positive and negative off-
sets are allowed. A subsequent fetch from that
address brings the data values into the chip.
SCRIPTS can directly execute operating sys-
tem I/O data structures, saving time at the
beginning of an I/O operation. The I/O data
structure can begin on any dword boundary
and may cross system segment boundaries.
There are two restrictions on the placement of
data in system memory:
1. The I/O data structure must lie within the 8
MB above or below the base address.
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