參數(shù)資料
型號(hào)： SMJ320C50GFA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 26/54頁(yè)
文件大?。?/td> 614K
代理商： SMJ320C50GFA
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
26
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
phase-locked loop (PLL) circuit timing
phase-locked loop characteristics using EXTCLK or on-chip crystal oscillator
PARAMETER
MIN
MAX
UNIT
F
pllin
F
pllout
I
pll
P
pll
PLL
dc
PLLJ
Frequency range, PLL input
5*
15*
MHz
Frequency range, PLL output
25*
75*
MHz
PLL current, CV
DD
supply
PLL power, CV
DD
supply
PLL output duty cycle at H1
2*
mA
5*
mW
45*
55*
%
PLL output jitter, F
pllout
= 25 MHz
PLL lock time in input cycles
400*
ps
PLL
LOCK
* Not production tested
Duty cycle is defined as 100*t
1
/(t
1
+t
2
)%
To ensure clean internal clock references, the minimal low and high pulse durations must be maintained. At high
frequencies, this may require a fast rise and fall time as well as a tightly controlled duty cycle. At lower
frequencies, these requirements are less restrictive when in x1 and x0.5 modes. The PLL, however, must have
an input duty cycle of between 40% and 60% for proper operation.
1000
cycles
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