參數(shù)資料
型號(hào)： SMJ320C50GFA
廠商： Texas Instruments, Inc.
元件分類(lèi)： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 47/54頁(yè)
文件大?。?/td> 614K
代理商： SMJ320C50GFA
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
47
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
general-purpose I/O timing
Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The contents of the internal
control registers associated with each peripheral define the modes for these pins.
peripheral pin I/O timing
The following table shows the timing parameters for changing the peripheral pin from a general-purpose output
pin to a general-purpose input pin and vice versa.
timing requirements for peripheral pin general-purpose I/O (see Note 1, Figure 34, and Figure 35)
MIN
MAX
UNIT
t
su(GPIO-H1L)
t
h(H1L-GPIO)
* Not production tested
NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Setup time, general-purpose input before H1 low
3*
ns
Hold time, general-purpose input after H1 low
0*
ns
switching characteristics over recommended operating conditions for peripheral pin
general-purpose I/O (see Note 1, Figure 34, and Figure 35)
PARAMETER
MIN
MAX
UNIT
t
d(H1H-GPIO)
Delay time, H1 high to general-purpose output
4
ns
t
dis(H1H)
NOTE 1: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1. The modes of these pins are defined by the contents
of internal-control registers associated with each peripheral.
Disable time, general-purpose output from H1 high
5
ns
Value on Pin
Seen in
Peripheral-
Control
Register
Synchronizer Delay
Buffers Go
From
Output to
Input
Execution
of Store of
Peripheral-
Control
Register
Data Bit
I/O
Control Bit
H1
H3
Output
Data
Seen
Data
Sampled
Peripheral Pin
(see Note A)
t
su(GPIO-H1L)
t
h(H1L-GPIO)
t
dis(H1H)
NOTE A: Peripheral pins include CLKX0, CLKR0, DX0, DR0, FSX0, FSR0, and TCLK0/1.
Figure 34. Change of Peripheral Pin From General-Purpose Output to Input Mode Timing
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