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參數(shù)資料
| 型號(hào)： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 12/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
12
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
PLL and clock oscillator control
The clock mode control pins are decoded into four operational modes as shown in Figure 4. These modes
control clock divide ratios, oscillator, and PLL power (see Table 2).
When an external clock input or crystal is connected, the opposite unused input is simply grounded. An XOR
gate then passes one of the two signal sources to the PLL stage. This allows the direct injection of a clock
reference into EXTCLK, or 1-20 MHz crystals and ceramic resonators with the oscillator circuit. The two clock
sources include:
A crystal oscillator circuit, where a crystal or ceramic resonator is connected across the XOUT and XIN pins
and EXTCLK is grounded.
An external clock input, where an external clock source is directly connected to the EXTCLK pin, and XOUT
is left unconnected and XIN is grounded.
When the PLL is initially started, it enters a transitional mode during which the PLL acquires lock with the input
signal. Once the PLL is locked, it continues to track and maintain synchronization with the input signal. The PLL
is a simple x5 reference multiplier with bypass and power control.
The clock divider, under CPU control, reduces the clock reference by 1 (MAXSPEED), 1/16 (LOWPOWER), or
clock stop (IDLE2). Wake-up from the IDLE2 state is accomplished by a RESET or interrupt pin logic-low state.
A divide-by-two TMS320C31 equivalent mode of operation is also provided. In this case, the clock output
reference is further divided by two with clock synchronization being determined by the timing of RESET falling
relative to the present H1/H3 state.
Clock Divider
PLL
Clock & Crystal OSC
CLKMD1
CLKMD0
PLL PWR and Bypass
Oscillator Enable
C31 DIV2 Mode
LOWPOWER
IDLE2
MAXSPEED/
CPU CLOCK
1/2
U
X
M
X1, 1/16, Off
á
XOR
SEL
X
U
M
PLL
X5
EXTCLK
XIN
XOUT
RF
S1
Figure 4. Clock Generation
Table 2. Clock Mode Select Pins
CLKMD0
CLKMD1
FEEDBACK
PLLPWR
RATIO
NOTES
0
0
Off
Off
1
Fully static, very low power
0
1
On
Off
1/2
Oscillator enabled
1
0
On
Off
1
Oscillator enabled
1
1
On
On
5
2 mA @ 60 MHz, 1.8 V PLL power. Oscillator enabled
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