- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365581 > SMJ320C50GFA (Texas Instruments, Inc.) DIGITAL SIGNAL PROCESSOR PDF資料下載
參數(shù)資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 40/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁當前第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
40
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
interrupt response timing
The following table defines the timing parameters for the INTx signals.
timing requirements for INT3-INT0 response (see Figure 28)
MIN
NOM
MAX
UNIT
t
su(INT-H1L)
t
h(H1L-INT)
t
w(INT)
* Not production tested
P = t
c(H)
The interrupt (INTx) pins are synchronized inputs that can be asserted at any time during a clock cycle. The
TMS320C3x interrupts
are
selectable as level- or edge-sensitive. Interrupts are detected on the falling edge of
H1. Therefore, interrupts must be set up and held to the falling edge of the internal H1 for proper detection. The
CPU and DMA respond to detected interrupts on instruction-fetch boundaries only.
Setup time, INT3- INT0 before H1 low
4*
ns
Hold time, INT3- INT0 after H1 low
0
ns
Pulse duration, interrupt to ensure only one interrupt
P + 5*
1.5P
2P - 5*
ns
For the processor to recognize only one interrupt when level mode is selected, an interrupt pulse must be set
up and held such that a logic-low condition occurs for:
A minimum of one H1 falling edge
No more than two H1 falling edges
Interrupt sources whose edges cannot be specified to meet the H1 falling edge setup and hold times must
be further restriced in pulse width as defined by t
w(INT)
(parameter 51) in the table above.
When EDGEMODE=1, the falling edge of the INT0-INT3 pins are detected using synchronous logic (see
Figure 7). The pulse low and high time should be two CPU clocks or greater.
The TMS320C3x can set the interrupt flag from the same source as quickly as two H1 clock cycles after it has
been cleared.
If the specified timings are met, the exact sequence shown in Figure 28 occurs; otherwise, an additional delay
of one clock cycle is possible.
相關PDF資料 |
PDF描述 |
|---|---|
| SMJ320VC33GNMM150 | DIGITAL SIGNAL PROCESSOR |
| SMJ320C25FJ | DIGITAL SIGNAL PROCESSOR |
| SMJ320C25GB | DIGITAL SIGNAL PROCESSOR |
| SMJ320C30GB | DIGITAL SIGNAL PROCESSOR |
| SMJ320C30HFG | DIGITAL SIGNAL PROCESSOR |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ320C50GFAM50 | 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 50MHZ 25MIPS 141CPGA - Trays |
| SMJ320C50GFAM66 | 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 66MHZ 33MIPS 141CPGA - Trays |
| SMJ320C50HFG | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSOR |
| SMJ320C50HFGM50 | 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 50MHZ 25MIPS 132CFPAK - Trays |
| SMJ320C50HFGM66 | 制造商:Texas Instruments 功能描述:5962-9455804QYA, 10K RAM, 2K ROM - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復。