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參數(shù)資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 49/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
49
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
timer pin timing
Valid logic-level periods and polarity are specified by the contents of the internal control registers. The following
tables define the timing parameters for the timer pin.
timing requirements for timer pin (see Figure 36 and Figure 37)
MIN
MAX
UNIT
t
su(TCLK-H1L)
t
h(H1L-TCLK)
* Not production tested
These requirements are applicable for a synchronous input clock.
Setup time, TCLK external before H1 low
3*
ns
Hold time, TCLK external after H1 low
0
ns
switching characteristics over recommended operating conditions for timer pin (see Figure 36 and
Figure 37)
PARAMETER
MIN
MAX
UNIT
t
d(H1H-TCLK)
Delay time, H1 high to TCLK internal valid
3
ns
t
c(TCLK)
Cycle time TCLK
Cycle time, TCLK
TCLK ext
t
c(H)
x 2.6*
t
c(H)
x 2*
t
c(H)
+ 5*
[t
c(TCLK)
/2] - 4*
ns
TCLK int
t
c(H)
x 2
32
*
t
w(TCLK)
Pulse duration TCLK
Pulse duration, TCLK
TCLK ext
TCLK int
ns
[t
c(TCLK)
/2] + 4*
* Not production tested
These parameters are applicable for an asynchronous input clock.
TCLK as input
H1
H3
t
su(TCLK-H1L)
t
h(H1L-TCLK)
t
h(H1L-TCLK)
t
su(TCLK-H1L)
t
w(TCLK)
t
c(TCLK)
Figure 36. Timer Pin Timing, Input
TCLK as output
H1
H3
t
d(H1H-TCLK)
t
d(H1H-TCLK)
Figure 37. Timer Pin Timing, Output
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