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參數(shù)資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 24/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
24
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
electrical characteristics over recommended ranges of supply voltage (unless otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP
§
MAX
UNIT
V
OH
V
OL
I
Z
I
I
I
IPU
I
IPD
I
BKU
I
BKD
High-level output voltage
DV
DD
= MIN,
DV
DD
= MIN,
T
C
= 25
°
C,
T
C
= 25
°
C,
Inputs with internal pullups
Inputs with internal pulldowns
I
OH
= MAX
I
OL
= MAX
DV
DD
= MAX
V
I
= V
SS
to DV
DD
2.4
V
Low-level output voltage
0.4
V
μ
A
μ
A
μ
A
μ
A
μ
A
μ
A
High-impedance current
-5
+5
Input current
-5
+5
Input current (with internal pullup)
-600
10
Input current (with internal pulldown)
Input current (with bus keeper) pullup
#
Input current (with bus keeper) pulldown
#
600
-10
Bus keeper opposes until conditions match
-600
10
600
-10
I
DDD
Supply current, pins
||
T
C
= 25
°
C,
DV
DD
= MAX
T
C
= 25
°
C,
CV
DD
= MAX
PLL enabled, oscillator enabled
f
x
= 75 MHz
25
260
mA
I
DDC
Supply current, core CPU
||
f
x
= 75 MHz
60
215
mA
2
mA
I
DD
IDLE2, Supply current, I
DDD
plus I
DDC
PLL disabled, oscillator enabled
500
PLL disabled, oscillator disabled, FCLK = 0
50
μ
A
C
i
Input capacitance
All inputs except XIN
10*
pF
XIN
10*
C
o
* Not production tested
All voltage values are with respect to V
SS
.
For test conditions shown as MIN, MAX, or NOM, use the appropriate value specified in the recommended operating conditions table.
§
For VC33, all typical values are at DV
DD
= 3.3, CV
DD
= 1.8 V, T
C
(case temperature) = 25
°
C.
Pins with internal pullup devices: TDI, TCK, and TMS. Pin with internal pulldown device: TRST.
#
Pins D0-D31 include internal bus keepers that maintain valid logic levels when the bus is not driven (see Figure 9).
||
Actual operating current is less than this maximum value. This value was obtained under specially produced worst-case test conditions, which
are not sustained during normal device operation. These conditions consist of continuous parallel writes of a checkerboard pattern at the
maximum rate possible. See
TMS320C3x General-Purpose Applications
(literature number SPRU194).
f
x
is the PLL output clock frequency.
Output capacitance
10*
pF
PARAMETER MEASUREMENT INFORMATION
Tester Pin
Electronics
V
Load
I
OL
CT
I
OH
Output
Under
Test
50
Where:
I
OL
I
O
and I
OH
are adjusted during ac timing analysis to achieve an ac termination of 50
V
LOAD
= DV
DD
/2
C
T
= 40-pF typical load-circuit capacitance
Figure 14. Test Load Circuit
= 4 mA (all outputs) for dc levels test.
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