參數(shù)資料
型號： SMJ320C50GFA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號處理器
文件頁數(shù)： 32/54頁
文件大?。?/td> 614K
代理商： SMJ320C50GFA
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
32
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
XF0 and XF1 timing when executing LDFI or LDII
The following tables define the timing parameters for XF0 and XF1 during execution of LDFI or LDII.
timing requirements for XF0 and XF1 when executing LDFI or LDII (see Figure 21)
MIN
MAX
UNIT
t
su(XF1-H1L)
t
h(H1L-XF1)
* Not production tested
Setup time, XF1 before H1 low
4*
ns
Hold time, XF1 after H1 low
0*
ns
switching characteristics over recommended operating conditions for XF0 and XF1 when executing
LDFI or LDII (see Figure 21)
PARAMETER
MIN
MAX
UNIT
t
d(H3H-XF0L)
Delay time, H3 high to XF0 low
3
ns
H3
H1
R/W
A[23:0]
D[31:0]
RDY
XF0
XF1
Fetch
LDFI or LDII
Decode
Read
Execute
PAGEx, STRB
t
d(H3H-XF0L)
t
su(XF1-H1L)
t
h(H1L-XF1)
Figure 21. Timing for XF0 and XF1 When Executing LDFI or LDII
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