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參數(shù)資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 42/54頁 |
| 文件大小： | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
42
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
interrupt-acknowledge timing
The IACK output goes active on the first half-cycle (HI rising) of the decode phase of the IACK instruction and
goes inactive at the first half-cycle (HI rising) of the read phase of the IACK instruction.
The following table defines the timing parameters for the IACK signal. The numbers shown in Figure 29
correspond with those in the NO. column of the table below.
NOTE:
The IACK instruction can be executed at anytime to signal an event. It is most often used within an
interrupt routine to signal which interrupt has occurred.
switching characteristics over recommended operating conditions for IACK (see Figure 29)
PARAMETER
MIN
-1*
MAX
3
UNIT
ns
t
d(H1H-IACKL)
t
d(H1H-IACKH)
* Not production tested
Delay time, H1 high to IACK low
Delay time, H1 high to IACK high
-1*
3
ns
H3
H1
IACK
ADDR
Data
Fetch IACK
Instruction
IACK Data
Read
Decode IACK
Instruction
t
d(H1H-IACKL)
t
d(H1H-IACKH)
Figure 29. Interrupt Acknowledge (IACK) Timing
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