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參數(shù)資料
| 型號(hào)： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 43/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
43
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
serial-port timing parameters
The following tables define the timing parameters for the serial port.
timing requirements (see Figure 30 and Figure 31)
MIN
MAX
UNIT
t
c(SCK)
Cycle time CLKX/R
Cycle time, CLKX/R
CLKX/R ext
t
c(H)
x 2.6*
t
c(H)
x 4*
t
c(H)
+ 5
[t
c(SCK)
/2] - 4*
ns
CLKX/R int
t
c(H)
x 2
16
*
t
w(SCK)
Pulse duration CLKX/R high/low
Pulse duration, CLKX/R high/low
CLKX/R ext
ns
CLKX/R int
[t
c(SCK)
/2] + 4*
3*
t
r(SCK)
t
f(SCK)
Rise time, CLKX/R
ns
Fall time, CLKX/R
3*
ns
t
su(DR-CLKRL)
Setup time DR before CLKR low
Setup time, DR before CLKR low
CLKR ext
4*
ns
CLKR int
5*
t
h(CLKRL-DR)
Hold time DR after CLKR low
Hold time, DR after CLKR low
CLKR ext
3*
ns
CLKR int
0*
t
su(FSR-CLKRL)
Setup time FSR before CLKR low
Setup time, FSR before CLKR low
CLKR ext
4*
ns
CLKR int
5*
t
h(SCKL-FS)
Hold time FSX/R input after CLKX/R low
Hold time, FSX/R input after CLKX/R low
CLKX/R ext
3*
ns
CLKX/R int
0*
t
su(FSX-CLKX)
Setup time external FSX before CLKX
Setup time, external FSX before CLKX
CLKX ext
CLKX int
-[t
c(H)
- 6]
-[t
c(H)
- 10]*
[t
c(SCK)
/2] - 6*
t
c(SCK)
/2*
ns
* Not production tested
A cycle time of t
c(H)
*2 is possible when the device is operated at lower CPU frequencies. See the
TMS320VC33 Silicon Update
(literature number
SPRZ176) for further details.
switching characteristics over recommended operating conditions (see Figure 30 and Figure 31)
PARAMETER
MIN
MAX
4*
UNIT
ns
t
d(H1H-SCK)
Delay time, H1 high to internal CLKX/R
t
d(CLKX-DX)
Delay time CLKX to DX valid
Delay time, CLKX to DX valid
CLKX ext
6
ns
CLKX int
5*
t
d(CLKX-FSX)
Delay time CLKX to internal FSX high/low
Delay time, CLKX to internal FSX high/low
CLKX ext
5
ns
CLKX int
4*
t
d(CLKX-DX)V
Delay time, CLKX to first DX bit, FSX precedes CLKX
high
CLKX ext
4
ns
CLKX int
5*
t
d(FSX-DX)V
t
dis(CLKX-DXZ)
* Not production tested
Delay time,
FSX to first DX bit, CLKX precedes FSX
Disable time, DX high impedance following last data bit from CLKX high
6
ns
6
ns
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