- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄365581 > SMJ320C50GFA (Texas Instruments, Inc.) DIGITAL SIGNAL PROCESSOR PDF資料下載
參數(shù)資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 15/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁當(dāng)前第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
15
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
EDGEMODE
When EDGEMODE = 1, a sampled digital delay line is decoded to generate a pulse on the falling edge of the
interrupt pin. To ensure interrupt recognition, input signal logic-high and logic-low states must be held longer
than the synchronizer delay of one CPU clock cycle. Holding these inputs to no less than two cycles in both the
logic-low and logic-high states is sufficient.
When EDGEMODE = 0, a logic-low interrupt pin will continually set the corresponding interrupt flag. The CPU
or DMA can clear this flag within two cycles of it being set. This is the maximum interrupt width that can be applied
if only one interrupt is to be recognized. The CPU can manually clear IF bits within an interrupt service routine
(ISR), effectively lengthening the maximum ISR width.
After reset, EDGEMODE is temporarily disabled, allowing logic-low INT pins to be detected for bootload
operation.
CPU Set
IF Bit
RESET
EDGEMODE
CPU Reset
INTn
H1
Delay
D
D Q
Q
Q
R
S
D Q
D Q
D Q
H3
Figure 7. EDGEMODE and Interrupt Flag CIrcuit
reset operation
When RESET is applied, the CPU attempts to safely exit any pending read or write operations that may be in
progress. This can take as much as 10 CPU cycles, after which, the address, data, and control pins will be in
an inactive or high-impedance state.
When both RESET and SHZ are applied, the device will immediately enter the reset state with the pins held in
high-impedance mode. SHZ should then be disabled at least 10 CPU cycles before RESET is set high. SHZ
can be used during power-up sequencing to prevent undefined address, data, and control pins, avoiding system
conflicts.
PAGE0 - PAGE3 select lines
To facilitate simpler and higher speed connection to external devices, the SM/SMJ320VC33 includes four
predecoded select pins that have the same timings as STRB. These pins are decoded from A22, A23, and STRB
and are active only during external accesses over the ranges shown in Table 4. All external bus accesses are
controlled by a single bus control register.
Table 4. PAGE0 - PAGE3 Ranges
START
0x000000
END
PAGE0
0x3FFFFF
PAGE1
0x400000
0x7FFFFF
PAGE2
0x800000
0xBFFFFF
PAGE3
0xC00000
0xFFFFFF
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SMJ320VC33GNMM150 | DIGITAL SIGNAL PROCESSOR |
| SMJ320C25FJ | DIGITAL SIGNAL PROCESSOR |
| SMJ320C25GB | DIGITAL SIGNAL PROCESSOR |
| SMJ320C30GB | DIGITAL SIGNAL PROCESSOR |
| SMJ320C30HFG | DIGITAL SIGNAL PROCESSOR |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SMJ320C50GFAM50 | 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 50MHZ 25MIPS 141CPGA - Trays |
| SMJ320C50GFAM66 | 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 66MHZ 33MIPS 141CPGA - Trays |
| SMJ320C50HFG | 制造商:TI 制造商全稱:Texas Instruments 功能描述:DIGITAL SIGNAL PROCESSOR |
| SMJ320C50HFGM50 | 制造商:Texas Instruments 功能描述:DSP FIX PT 16BIT 50MHZ 25MIPS 132CFPAK - Trays |
| SMJ320C50HFGM66 | 制造商:Texas Instruments 功能描述:5962-9455804QYA, 10K RAM, 2K ROM - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。