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參數(shù)資料
| 型號(hào)： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號(hào)處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號(hào)處理器 |
| 文件頁數(shù)： | 33/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
33
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
XF0 timing when executing STFI and STII
The following table defines the timing parameters for the XF0 pin during execution of STFI or STII.
switching characteristics over recommended operating conditions for XF0 when executing STFI
or STII (see Figure 22)
PARAMETER
MIN
MAX
UNIT
t
d(H3H-XF0H)
XF0 is always set high at the beginning of the execute phase of the interlock-store instruction. When no pipeline conflicts occur, the address of
the store is also driven at the beginning of the execute phase of the interlock-store instruction. However, if a pipeline conflict prevents the store
from executing, the address of the store will not be driven until the store can execute.
Delay time, H3 high to XF0 high
3
ns
H3
H1
PAGEx, STRB
R/W
A[23:0]
D[31:0]
RDY
XF0
Fetch
STFI or STII
Read
Execute
Decode
t
d(H3H-XF0H)
Figure 22. Timing for XF0 When Executing an STFI or STII
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