參數(shù)資料
型號(hào)： SMJ320C50GFA
廠商： Texas Instruments, Inc.
元件分類： 數(shù)字信號(hào)處理
英文描述： DIGITAL SIGNAL PROCESSOR
中文描述： 數(shù)字信號(hào)處理器
文件頁(yè)數(shù)： 14/54頁(yè)
文件大?。?/td> 614K
代理商： SMJ320C50GFA
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
14
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
PLL isolation
The internal PLL supplies can be directly connected to CV
DD
and V
SS
(0
case) or fully isolated as shown in
Figure 6. The RC network prevents the PLL supplies from turning high frequency noise in the CV
DD
and V
SS
supplies into jitter.
CV
DD
0 -100
0.1
μ
F
0.01
μ
F
0 -100
V
SS
PLLV
DD
PLLV
SS
Figure 6. PLL Isolation Circuit Diagram
clock and PLL considerations on initialization
On power up, the CPU clock divide mode can be in MAXSPEED, LOPOWER or IDLE2, or the PLL could be
in an undefined mode. RESET falling in the presence of a valid CPU clock is used to clear this state, after which
the device will synchronously terminate any external activity.
The 5x Fclkin PLL of the 320VC33 contains an 8-bit PLL-LOCK counter that will cause the PLL to output a
frequency of Fclkin/2 during the initial ramp. This counter, however, does not increment while RESET is low or
in the absence of an input clock. A minimum of 256 input clocks are required before the first falling edge of reset
for the PLL to output to clear this counter. The setup and behavior that is seen is as follows.
Power is applied to the DSP with RESET low and the input clock high or low. A clock is applied (RESET is still
low) and the PLL appears to lock on to the input clock, producing the expected x5 output frequency. RESET
is driven high and the PLL output immediately drops to Fclkin/2 for up to 256 input cycles or 128 of the Fclkin/2
output cycles. The PLL/CPU clock then switches to x5 mode.
The switch over is synchronous and does not create a clock glitch, so the only effect is that the CPU will run
slow for up to the first 128 cycles after reset goes high. Once the PLL has stabilized, the counter will remain
cleared and subsequent resets will not exhibit this condition.
power sequencing considerations
Though an internal ESD and CMOS latchup protection diode exists between CV
DD
and DV
DD
, it should not be
considered a current-carrying device on power up. An external Schottky diode should be used to prevent CV
DD
from exceeding DV
DD
by more than 0.7 V. The effect of this diode during power up is that if CV
DD
is powered
up first, DV
DD
will follow by one diode drop even when the DV
DD
supply is not active.
Typical systems using LDOs of the same family type for both DV
DD
and CV
DD
will track each other during power
up. In most cases, this is acceptable; but if a high-impedance pin state is required on power up, the SHZ pin
can be used to asynchronously disable all outputs. RESET should not be used in this case since some signals
require an active clock for RESET to have an effect and the clock may not yet be active. The internal core logic
becomes functional at approximately 0.8 V while the external pin IO becomes active at about 1.5 V.
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