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參數(shù)資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 38/54頁 |
| 文件大小： | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
38
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
reset timing
RESET is an asynchronous input that can be asserted at any time during a clock cycle. If the specified timings
are met, the exact sequence shown in Figure 27 occurs; otherwise, an additional delay of one clock cycle is
possible.
The asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
Resetting the device initializes the bus control register to seven software wait states and therefore results in slow
external accesses until these registers are initialized.
HOLD is a synchronous input that can be asserted during reset. It can take nine CPU cycles before HOLDA
is granted.
The following table defines the timing parameters for the RESET signal. The numbers shown in Figure 27
correspond with those in the NO. column of the following table.
timing requirements for RESET (see Figure 27)
MIN
MAX
P - 7
*
UNIT
t
su(RESET-EXTCLKL)
t
su(RESETH-H1L)
* Not production tested
P = t
c(EXTCLK)
Setup time, RESET before EXTCLK low
5*
ns
Setup time, RESET high before H1 low and after ten H1 clock cycles
5
ns
switching characteristics over recommended operating conditions for RESET (see Figure 27)
PARAMETER
MIN
*
MAX
*
UNIT
t
d(EXTCLKH-H1H)
t
d(EXTCLKH-H1L)
t
d(EXTCLKH-H3L)
t
d(EXTCLKH-H3H)
t
dis(H1H-DZ)
t
dis(H3H-AZ)
t
d(H3H-CONTROLH)
t
d(H1H-RWH)
t
d(H1H-IACKH)
Delay time, EXTCLK high to H1 high
2
7
ns
Delay time, EXTCLK high to H1 low
2
7
ns
Delay time, EXTCLK high to H3 low
2
7
ns
Delay time, EXTCLK high to H3 high
Disable time, Data (high impedance) from H1 high
2
7
ns
6
ns
Disable time, Address (high impedance) from H3 high
6
ns
Delay time, H3 high to control signals high
3
ns
Delay time, H1 high to R/W high
3
ns
Delay time, H1 high to IACK high
Disable time, Asynchronous reset signals disabled (high impedance) from
RESET
low
§
3
ns
t
dis(RESETL-ASYNCH)
6
ns
* Not production tested
High impedance for Dbus is limited to nominal bus keeper Z
OUT
= 15 k
.
§
Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
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