參數(shù)資料
型號(hào): SMJ320C50GFA
廠(chǎng)商: Texas Instruments, Inc.
元件分類(lèi): 數(shù)字信號(hào)處理
英文描述: DIGITAL SIGNAL PROCESSOR
中文描述: 數(shù)字信號(hào)處理器
文件頁(yè)數(shù): 41/54頁(yè)
文件大?。?/td> 614K
代理商: SMJ320C50GFA
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
41
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
interrupt response timing (continued)
Reset or
Interrupt
Vector Read
Fetch First
Instruction of
Service
Routine
H3
H1
INT3 - INT0 Pin
(EDGEMODE = 0)
INT3 - INT0
Flag
ADDR
Data
Vector Address
First Instruction Address
INT3 - INT0 Pin
(EDGEMODE = 1)
t
su(INT-H1L)
t
su(INT-H1L)
t
h(H1L-INT)
t
su(INT-H1L)
t
w(INT)
§
Falling edge of H1 just detects INTx falling edge.
Falling edge of H1 detects second INTx low, however flag clear takes precedence.
§
Nominal width.
Falling edge of H1 misses previous INTx low as INTx rises.
Figure 28. INT3-INT0 Response Timing
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