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參數資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數字信號處理器 |
| 文件頁數： | 45/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
45
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
HOLD timing
HOLD is a synchronous input that can be asserted at any time during a clock cycle. If the specified timings are
met, the exact sequence shown in Figure 32 and Figure 33 occurs; otherwise, an additional delay of one clock
cycle is possible.
The table, “timing parameters for HOLD/HOLDA”, defines the timing parameters for the HOLD and HOLDA
signals. The numbers shown in Figure 32 and Figure 33 correspond with those in the NO. column of the table.
The NOHOLD bit of the primary-bus control register overrides the HOLD signal. When this bit is set, the device
comes out of hold and prevents future hold cycles.
Asserting HOLD prevents the processor from accessing the primary bus. Program execution continues until a
read from or a write to the primary bus is requested. In certain circumstances, the first write is pending, thus
allowing the processor to continue (internally) until a second external write is encountered.
Figure 32, Figure 33, and the accompaning timings are for a zero wait-state bus configuration. Since HOLD is
internally captured by the CPU on the H1 falling edge one cycle before the present cycle is terminated, the
minimum HOLD width for any bus configuration is, therefore, WTCNT+3. Also, HOLD should not be deasserted
before HOLDA has been active for at least one cycle.
timing requirements for HOLD/HOLDA (see Figure 32 and Figure 33)
MIN
MAX
UNIT
t
su(HOLD-H1L)
t
w(HOLD)
*Not production tested.
Setup time, HOLD before H1 low
3
ns
Pulse duration, HOLD low
3t
c(H)
*
ns
switching characteristics over recommended operating conditions for HOLD/HOLDA
(see Figure 32 and Figure 33)
PARAMETER
MIN
MAX
UNIT
t
v(H1L-HOLDA)
t
w(HOLDA)
t
d(H1L-SH)H
t
dis(H1L-S)
t
en(H1L-S)
t
dis(H1L-RW)
t
en(H1L-RW)
t
dis(H1L-A)
t
en(H1L-A)
t
dis(H1H-D)
* Not production tested
Valid time, HOLDA after H1 low
-1*
3*
ns
Pulse duration, HOLDA low
2t
c(H)
- 4*
-1
ns
Delay time, H1 low to STRB high for a HOLD
3
ns
Disable time, STRB to the high-impedance state from H1 low
4
ns
Enable time, STRB enabled (active) from H1 low
4
ns
Disable time, R/W to the high-impedance state from H1 low
5*
ns
Enable time, R/W enabled (active) from H1 low
4
ns
Disable time, Address to the high-impedance state from H1 low
4*
ns
Enable time, Address enabled (valid) from H1 low
5
ns
Disable time, Data to the high-impedance state from H1 high
4*
ns
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