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| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 13/54頁 |
| 文件大小： | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
13
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
PLL and clock oscillator control (continued)
Typical crystals in the 8-30 MHz range have a series resistance of 25
,
which increases below 8 MHz. To
maintain proper filtering and phase relationships, R
d
and Z
out
of the oscillator circuit should be 10x-40x that of
the crystal. A series compensation resistor (Rd), shown in Figure 5, is recommended when using lower
frequency crystals. The XOUT output, the square wave inverse of XIN, is then filtered by the XOUT output
impedance, C1 load capacitor, and R
d
(if present). The crystal and C2 input load capacitor then refilters this
signal, resulting in a XIN signal that is 75-85% of the oscillator supply voltage.
NOTE:
Some ceramic resonators are available in a low-cost, three-terminal package that includes C1 and C2
internally. Typically, ceramic resonators do not provide the frequency accuracy of crystals.
NOTE:
Better PLL stability can be achieved using the optional power supply isolation circuit shown in Figure 5.
A similar filter can be used to isolate the PLLV
SS
, as shown in Figure 6. PLLV
DD
can also be directly connected
to CV
DD
.
Table 3. Typical Crystal Circuit Loading
FREQUENCY (MHz)
Rd (
)
4.7k
C1 (pF)
C2 (pF)
CL
(pF)
RL
(
)
200
2
18
18
12
5
2.2k
18
18
12
60
10
470
15
15
12
30
15
0
15
12
12
25
20
0
9
9
10
25
CL and RL are typical internal series load capacitance and resistance of the crystal.
XOUT
XIN
C1
C2
Crystal
EXTCLK
Rd
PLLV
SS
CV
DD
100
PLLV
DD
0.1
μ
F
0.01
μ
F
Figure 5. Self-Oscillation Mode
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