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參數資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數字信號處理器 |
| 文件頁數： | 28/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
28
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
clock circuit timing (continued)
The following tables define the timing requirements and switching characteristics for EXTCLK.
timing requirements for EXTCLK, all modes (see Figure 16 and Figure 17)
MIN
MAX
1*
UNIT
t
r(EXTCLK)
Rise time EXTCLK
Rise time, EXTCLK
F = F
max
, x0.5 and x1 modes
F < F
max
F = F
max
, x0.5 and x1 modes
F < F
max
x5 mode
ns
4*
t
f(EXTCLK)
Fall time EXTCLK
Fall time, EXTCLK
1*
ns
4*
21*
t
w(EXTCLKL)
Pulse duration, EXTCLK low
x1 mode
6*
ns
x0.5 mode
4*
x5 mode
21*
t
w(EXTCLKH)
Pulse duration, EXTCLK high
x1 mode
5*
ns
x0.5 mode
4*
x5 PLL mode
40*
60*
t
dc(EXTCLK)
Duty cycle, EXTCLK [t
w(EXTCLKH)
/ t
c(H)]
x1 and x0.5 modes, F = max
45
55
%
x1 and x0.5 modes, F = 0 Hz
0*
100*
x5 mode
66.7*
200*
t
c(EXTCLK)
Cycle time, EXTCLK
x1 mode
13.3
ns
x0.5 mode
10*
x5 mode
5*
15*
F
ext
Frequency range, 1/t
c(EXTCLK)
x1 mode
0
75
MHz
x0.5 mode
0*
100*
* Not production tested
switching characteristics for EXTCLK over recommended operating conditions, all modes
(see Figure 16 and Figure 17)
PARAMETER
MIN
TYP
MAX
UNIT
V
mid
Mid-level, used to measure duty cycle
0.5 x DV
DD
4.5
V
t
d(EXTCLK-H)
Delay time, EXTCLK to H1 and
H3
x1 mode
2*
7*
ns
x0.5 mode
2*
4.5
7*
t
r(H)
t
f(H)
t
d(HL-HH)
Rise time, H1 and H3
3*
ns
Fall time, H1 and H3
3*
ns
Delay time, from H1 low to H3 high or from H3 low to H1 high
-1.5*
2*
ns
x5 PLL mode
1/(5 x fext)
t
c(H)
Cycle time, H1 and H3
x1 mode
1/fext
ns
x0.5 mode
2/fext
* Not production tested
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