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參數(shù)資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 39/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
39
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
reset timing (continued)
EXTCLK
H1
t
d(EXTCLKH-H3L)
H3
RESET
(see Notes A and C)
IACK
D[31:0]
PAGEx, A[23:0]
STRB
Asynchronous
Reset Signals
(see Note B)
R/W
Ten H1 Clock Cycles
t
dis(H1H-DZ)
t
su(RESET-EXTCLKL)
t
d(EXTCLKH-H1H)
t
d(EXTCLKH-H1L)
t
su(RESETH-H1L)
t
d(EXTCLKH-H3H)
t
d(H3H-CONTROLH)
t
dis(H3H-AZ)
t
d(H1H-RWH)
t
d(H1H-IACKH)
t
dis(RESETL-ASYNCH)
NOTES: A. Clock circuit is configured in C31-compatible divide-by-2 mode. If configured for x1 mode, EXTCLK directly drives H3.
B. Asynchronous reset signals include XF0/1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, and TCLK0/1.
C. RESET is a synchronous input that can be asserted at any point during a clock cycle. If the specified timings are met, the exact
sequence shown occurs; otherwise, an additional delay of one clock cycle is possible.
D. In microprocessor mode, the reset vector is fetched twice, with seven software wait states each time. In microcomputer mode, the
reset vector is fetched twice, with no software wait states.
E. The address and PAGE3-PAGE0 outputs are placed in a high-impedance state during reset requiring a nominal 10-22 k
pullup.
If not, undesirable spurious reads can occur when these outputs are not driven.
Figure 27. RESET Timing
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