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參數資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數字信號處理器 |
| 文件頁數： | 16/54頁 |
| 文件大?。?/td> | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
16
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
using external logic with the READY pin
The key to designing external wait-state logic is the internal bus control register and associated internal logic
that logically combines the external READY pin with the much faster on-chip bus control logic. This essentially
allows slow external logic to interact with the bus while easily meeting the READY input timings. It is also relevant
to mention that the combined ready signals are sampled on the rising edge of the internal H1 clock. Please refer
to Figure 8 for the following examples.
example 1
A simple 0 or WTCNT wait-state decoder can be created by simply tying an address line back to the READY
pin and selecting the AND option. When the tied back address is low, the bus will run with 0 wait states. When
the tied back address is high, the bus will be controlled by the internal wait-state counter.
By enabling the bank compare logic, proper operation is further ensured by inserting a null cycle before a read
on the next bank is performed (writes are not pre-extended). This extra time can also be used by external logic
to affect the feedback path.
example 2
An N-WTCNT minimum wait-state decoder can also be created by tying back an address line to READY and
logically ORing it with the internal bank compare and wait count signals. When the address pin is low, bus timing
is determined by the internal WTCNT and BNKCMP settings. When the address line is high, the bus can run
no faster than the WTCNT counter and will be extended as long as READY is held high.
D Q
H3
Abus
N-Bit
Bank
Compare
Abus_old
N_Wait
Counter
R
H3
D
Q
H1
BUS_READY
1
2
3
0
PAGE_0
PAGE_1
PAGE_2
PAGE_3
Decode
A23
A22
Bus_Enable_Strobe,
0 = Active
Pins
Device
Enable
STRB Pin
READY Pin
R/W Pin
R/W
0 = Bus Idle
To C31 Style
Decoder
(C31 Compatibility)
E
Figure 8. Internal Ready Logic, Simplified Diagram
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