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參數(shù)資料
| 型號： | SMJ320C50GFA |
| 廠商： | Texas Instruments, Inc. |
| 元件分類： | 數(shù)字信號處理 |
| 英文描述： | DIGITAL SIGNAL PROCESSOR |
| 中文描述： | 數(shù)字信號處理器 |
| 文件頁數(shù)： | 17/54頁 |
| 文件大小： | 614K |
| 代理商： | SMJ320C50GFA |
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SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
17
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
example 2 (continued)
Table 5. MUX Select (Bus Control Register Bits 4 and 3)
BIT 4
BIT 3
RESULTS
0
0
Ignore internal wait counter and use only external READY
0
1
Use only internal wait counter and ignore ready pin
1
0
Logically AND internal wait counter with ready pin
1
1
Logically OR internal wait counter with ready pin (reset default)
posted writes
External writes are effectively “posted” to the bus, which then acts like an output latch until the write completes.
Therefore, if the application code is executing internally, it can perform a very slow external write with no penalty
since the bus acts like it has a one-level-deep write FIFO.
data bus I/O buffer
The circuit shown in Figure 9 is incorporated into each data pin to lightly “hold” the last driven value on the data
bus pins when the DSP or an external device is not actively driving the bus. Each bus keeper is built from a
three-state driver with nominal 15 k
output resistance which is fed back to the input in a positive feedback
configuration. The resistance isolated driver then pulls the output in one direction or the other keeping the last
driven value. This circuit is enabled in all functional modes and is only disabled when SHZ is pulled low.
30
15 k
SHZ
Bus keeper
Internal
Data Bus
R/W
External Data
Bus Pin
Figure 9. Bus Keeper Circuit
For an external device to change the state of these pins, it must be able to drive a small dc current until the driver
threshold is crossed. At the crossover point, the driver changes state, agreeing with the external driver and
assisting the change. The voltage threshold of the bus keeper is approximately at 50% of the DV
DD
supply
voltage. The typical output impedance of 30
for all SM/SMJ320VC33 I/O pins is easily capable of meeting
this requirement.
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