參數(shù)資料
型號: SMJ320C50GFA
廠商: Texas Instruments, Inc.
元件分類: 數(shù)字信號處理
英文描述: DIGITAL SIGNAL PROCESSOR
中文描述: 數(shù)字信號處理器
文件頁數(shù): 50/54頁
文件大?。?/td> 614K
代理商: SMJ320C50GFA
SM320VC33, SMJ320VC33
DIGITAL SIGNAL PROCESSOR
SGUS034E - FEBRUARY 2001 - REVISED OCTOBER 2002
50
POST OFFICE BOX 1443
HOUSTON, TEXAS 77251-1443
SHZ pin timing
The following table defines the timing parameter for the SHZ pin.
switching characteristics over recommended operating conditions for SHZ (see Figure 38)
PARAMETER
MIN
MAX
UNIT
t
dis(SHZ)
* Not production tested
Disable time, SHZ low to all outputs, I/O pins disabled (high impedance)
0*
8*
ns
SHZ
All I/O Pins
t
dis(SHZ)
NOTE A: Enabling SHZ destroys SM/SMJ320VC33 register and memory contents.
Assert SHZ = 1 and reset the SM/SMJ320VC33 to restore it to a known
condition.
Figure 38. Timing for SHZ
test access port timing
The following table defines the timing parameter for the test access port.
timing for test access port (see Figure 39)
MIN
5*
MAX
UNIT
ns
t
su(TMS-TCKH)
t
h(TCKH-TMS)
t
d(TCKL-TDOV)
t
r (TCK)
Setup time, TMS/TDI to TCK high
Hold time, TMS/TDI from TCK high
5*
ns
Delay time, TCK low to TDO valid
0*
10*
ns
Rise time, TCK
3*
ns
t
f (TCK)
* Not production tested
Fall time, TCK
3*
ns
TCK
TMS/TDI
TDO
t
d(TCHL-TDOV)
t
su(TMS-TCKH)
t
h(TCHK-TMS)
t
r(TCK)
t
f(TCK)
Figure 39. IEEE-1149.1 Test Access Port Timings
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