參數(shù)資料
型號： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 78/88頁
文件大?。?/td> 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
8
1 Overview
The Silicon Image SiI3124 is a four-port PCI-X to Serial ATA controller. The SiI3124 is designed to provide multiple port serial
ATA connectivity with minimal host overhead and host to device latency. The SiI3124 supports a 64-bit 133 MHz PCI-X bus
and the Serial ATA Generation 2 transfer rate of 3.0 Gb/s (300 MB/s).
1.1 Features
1.1.1
Overall Features
Host Protocol
o
Optimized for transaction oriented designs – minimal Host overhead
o
Supports two command issuance mechanisms
Efficient in both embedded and PC implementations
Reduces dependency on bridge behavior
o
Designed to leverage PCI-X burst capabilities
o
Full 64 bit functionality
Supports up to 4Mbit external Flash for BIOS expansion
Supports a multimaster I2C interface
Supports external Flash or serial EEPROM for programmable subsystem vendor ID / subsystem product ID
Fabricated in a 0.18μ CMOS process with a 1.8 volt core and 3.3 volt I/Os
Available in a 364-pin HSBGA package (21x21 mm, 1mm ball pitch)
JTAG boundary scan
1.1.2
PCI-X Features
Supports 133 MHz PCI-X with 64-bit data
Internal application interface multiplexed to 4 ports
All registers appear in unified memory space
Full-chip command completion status accessible with single PCI-X burst access
I/O port access to register space
1.1.3
Serial ATA Features
Integrated Serial ATA Link and PHY logic
Compliant with Serial ATA 1.0 and Serial ATA II Extensions to Serial ATA 1.0 Specifications
Supports Serial ATA Generation 2 transfer rate of 3.0 Gb/s
Supports Serial ATA II: Port Multiplier 1.0 Specifications
Plesiochronous, Single PLL architecture, 1 PLL for 4 ports
Output Swing Control
Supports four independent Serial ATA channels
o
Independent Link, Transport, and data FIFO
o
Independent command fetch, scatter/gather, and command execution
Hard coded state machines – no code space or download
o
Supports Legacy Command Queuing (LCQ)
o
Supports Native Command Queuing (NCQ)
o
Supports Non-zero offsets NCQ
o
Supports Out of order data delivery NCQ
o
Supports FIS-based switching with Port Multipliers
31 Commands and Scatter/Gather Tables per Port on-chip
Supports asynchronous notification
Protocol Override per Command
Staggered Spin-up Control
Supports Far End Retimed Loopback BIST
1.2 References
Serial ATA / High Speed Serialized AT Attachment specification, Revision 1.0
Serial ATA II: Extensions to Serial ATA 1.0 Specification
PCI Local Bus Specification Revision 2.3
PCI-X Addendum to the Local PCI Bus Specification Revision 1.0a
Serial ATA II: Port Multiplier 1.0 Specification
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