參數(shù)資料
型號(hào)： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 66/88頁
文件大?。?/td> 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
69
7.3.3
Port Control Set
Address Offset: Set: 1000H
Access Type: Write One To Set
Reset Value: N/A
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
OOB
Bypas
s
Reserved
LED
On
A
u
to
Int
e
rlock
A
c
cep
t
PM
Enable
Int
e
rlock
A
c
cept
Int
e
rlock
R
e
je
c
t
3
2
-bi
tAc
ti
v
a
ti
on
Scrambl
e
Dis
a
ble
CONT
Dis
a
ble
Transmit
BIST
Re
s
u
me
Pac
ket
Length
LE
D
Dis
a
b
le
Inte
rrupt
NCoR
Port
Init
ializ
e
De
v
ice
Re
se
t
Port
R
e
set
This register is used to direct various port operations. A one written to a bit position sets that bit in the control register.
Bit [31:26,24:16,6]
: Reserved (R). These bits are reserved.
Bit [25]
: OOB Bypass (W1S). If this bit is set, the Link will bypass the OOB initialization sequence following a
reset. This bit is reset by Global Reset, and not reset by Port Reset.
Bit [15]
: LED On (W1S). This bit turns on the LED Port Activity indicator regardless of the state of LED Disable
(bit 4).
Bit [14]
: Auto Interlock Accept (W1S). When this bit is set the link will accept any interlocked FIS reception.
The link will transmit R_OK in response to the received FIS.
Bit [13]
: PM Enable (W1S). This bit enables Port Multiplier support.
Bit [12]
: Interlock Accept (W1S). This bit is used to signal the link to accept an interlocked FIS reception. The
link will transmit R_OK in response to the received FIS. This bit is self-clearing.
Bit [11]
: Interlock Reject (W1S). This bit is used to signal the link to reject an interlocked FIS reception. The
link will transmit R_ERR in response to the received FIS. This bit is self-clearing.
Bit [10]
: 32-bit Activation (W1S). When this bit is set to one, a write to the low 32 bits of a Command Activation
register will cause the 32-bit Activation Upper Address register contents to be written to the upper 32 bits of the
Command Activation register and will trigger command execution. When this bit is zero, a write to the upper 32
bits or all 64 bits of a command activation register is required to trigger command execution. This bit is set for
environments that do not address more than 2
32 bytes of host memory.
Bit [9]
: Scrambler Disable (W1S). When this bit is set to one, the Link scrambler operation is disabled.
Bit [8]
: CONT Disable (W1S). When this bit is set to one, the Link will not generate a CONT following repeated
primitives.
Bit [7]
: Transmit BIST (W1S). This bit causes transmission of a BIST FIS.
Bit [6]
: Resume (W1S).
Bit [5]
: Packet Length (W1S). This bit directs the length of the packet command to be sent for commands with
packet protocol. When this bit is zero, a 12-byte packet will be sent. When this bit is one, a 16-byte packet will
be sent. This bit should be set to the same value as derived from word 0 of the identify packet command
returned data.
Bit [4]
: LED Disable (R/W). This bit disables the operation of the LED Port Activity indicator.
Bit [3]
: Interrupt No Clear on Read (W1S). When this bit is set to one, a command completion interrupt may be
cleared only by writing a one to the Command Completion bit in the Port Interrupt Status register. When this bit
is zero, reading the Port Slot Status register may also be used to clear the Command Completion interrupt.
Bit [2]
: Port Initialize (W1S). Setting this bit to one causes all commands to be flushed from the port and all
command execution parameters to be set to an initialized state. Setting this bit to one causes the port ready bit
in the port status register to be cleared to zero. When the initialization procedure is complete, the port ready bit
will be set to one. This bit is self-clearing and will be cleared upon execution by the port.
Bit [1]
: Device Reset (W1S). Setting this bit to one causes all commands to be flushed from the port and all
command execution parameters to be set to an initialized state. Setting this bit to one causes the port ready bit
in the port status register to be cleared to zero. The port will generate the COMRESET primitive on the serial
ATA bus. When the out of band sequence and initialization procedure is complete, the port ready bit will be set
to one. This bit is self-clearing and will be cleared upon execution by the port.
Bit [0]
: Port Reset (W1S). Setting this bit to one causes the port to be held in a reset state. No commands will
be executed while in this state. All port registers and functions are reset to their initial state, except as noted
below. All commands are flushed from the port and all command execution parameters are set to an initialized
state. Setting this bit to one causes the port ready bit in the port status register to be cleared to zero. Upon
setting this bit to zero from an asserted state, the port will generate the COMRESET primitive on the serial ATA
bus. When the out of band sequence and initialization procedure is complete, the port ready bit will be set to
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