參數(shù)資料
型號： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 56/88頁
文件大小： 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
6
Table of Tables
Table 2-1 Absolute Maximum Ratings.........................................................................................................................................9
Table 2-2 DC Specifications .......................................................................................................................................................10
Table 2-3 SATA Interface DC Specifications..............................................................................................................................10
Table 2-4 SATA Interface Timing Specifications ........................................................................................................................11
Table 2-5 SATA Interface Transmitter Output Jitter Characteristics, 1.5 Gb/s ...........................................................................11
Table 2-6 SATA Interface Transmitter Output Jitter Characteristics, 3 Gb/s ..............................................................................11
Table 2-7 CLKI SerDes Reference Clock Input Requirements...................................................................................................12
Table 2-8 Power Supply Noise Requirements............................................................................................................................12
Table 2-9 PCI 33 MHz Timing Specifications .............................................................................................................................12
Table 2-10 PCI 66 MHz Timing Specifications ...........................................................................................................................13
Table 2-11 PCI-X 133 MHz Timing Specifications .....................................................................................................................13
Table 3-1 SiI3124A Pin Listing ...................................................................................................................................................14
Table 3-2 Pin Types ...................................................................................................................................................................17
Table 5-1 Scatter/Gather Entry (SGE)........................................................................................................................................28
Table 5-2 Scatter/Gather Table (SGT) .......................................................................................................................................29
Table 5-3 Control Field Bit Definitions ........................................................................................................................................31
Table 5-4 Protocol Override Bit Definitions ................................................................................................................................32
Table 5-5 Port Request Block For Standard ATA Commands ...................................................................................................33
Table 5-6 PRB FIS Area Definition.............................................................................................................................................34
Table 5-7 Port Request Block For PACKET Command .............................................................................................................35
Table 5-8 Port Request Block For Soft Reset Command ...........................................................................................................36
Table 5-9 Port Request Block For External Commands.............................................................................................................37
Table 5-10 Port Request Block For Receiving Interlocked FIS ..................................................................................................38
Table 5-11 Interrupt Steering .....................................................................................................................................................41
Table 5-12 Port Interrupt Causes And Control ...........................................................................................................................44
Table 6-1 Auto-Initialization from Flash Timing ..........................................................................................................................48
Table 6-2 Flash Data Description ...............................................................................................................................................48
Table 6-3 Auto-Initialization from EEPROM Timing ...................................................................................................................49
Table 6-4 Auto-Initialization from EEPROM Timing Symbols.....................................................................................................49
Table 6-5 EEPROM Data Description ........................................................................................................................................49
Table 7-1 SiI3124A PCI Configuration Space ............................................................................................................................50
Table 7-2 SiI3124A Internal Register Space – Base Address 0 .................................................................................................60
Table 7-3 PCI bus Mode ............................................................................................................................................................62
Table 7-4 SiI3124A Internal Register Space – Base Address 1 .................................................................................................67
Table 7-5 Port LRAM layout .......................................................................................................................................................68
Table 7-6 Port LRAM Slot layout ................................................................................................................................................68
Table 7-7 Command Error Codes ..............................................................................................................................................74
Table 7-8 Default FIS Configurations .........................................................................................................................................75
Table 7-9 SError Register Bits (DIAG Field)...............................................................................................................................82
Table 7-10 SiI3124A Internal Register Space – Base Address 2 ...............................................................................................83
Table 8-1 Power Management Register Bits..............................................................................................................................84
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