參數(shù)資料
型號(hào)： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁(yè)數(shù)： 24/88頁(yè)
文件大?。?/td> 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
30
The PRB can take various forms, depending on the type of command being issued. The command types are:
Standard ATA Commands.
This includes all the common ATA commands such as READ SECTORS, WRITE SECTORS, READ DMA,
WRITE DMA, IDENTIFY DEVICE, SMART, etc. Also included are the queued commands in both legacy and
SATA native queue modes. For these commands, the PRB contains the entire “Register – Host to Device” FIS
containing the ATA command. By default, the SiI3124 decodes the ATA command type and executes the
necessary SATA protocol automatically. The host driver may, optionally, execute any desired SATA protocol on
a per-command basis.
PACKET Commands.
ATAPI PACKET commands operate in a similar fashion to the standard ATA commands. The “Register – Host
to Device” FIS contains the ATA PACKET command. The 12 or 16-byte ATAPI command is placed in the area
normally reserved for the first SGE. The SiI3124 does not decode the contents of the 12 or 16-byte ATAPI
command, so the host driver indicates the direction of any data transfer associated with the command.
Soft Reset
A special form of the PRB instructs the SiI3124 to transmit a soft reset sequence to a device. The SiI3124
creates the necessary “Register – Host to Device” FISes required for the sequence. No SGEs are required for
this PRB type. Other than the control field, the only item that needs to be populated is the PMP field, to direct
the soft reset sequence to the proper device in the event that a port multiplier is attached. Upon successful
command completion, the “Register – Device to Host” FIS is available in the command slot, allowing the host
driver to view the device signature.
External Command
The external command feature allows the host driver to transmit any arbitrary FIS that will not fit in the FIS area
of the PRB. This feature is useful in custom applications that have a need to send large FISes or Data FISes in
a fashion that does not comply with the defined SATA protocol
Interlocked FIS Reception
The interlocked FIS feature allows the host driver to receive any desired FIS type directly to a host memory
buffer, bypassing all SATA protocol for that FIS type. To use this feature, the host first specifies the FIS type(s)
to be interlocked. Then, any number of available command slots can be reserved for the reception of FISes
matching the defined type(s).
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