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參數(shù)資料
| 型號(hào)： | SII3124ACBHU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA364 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364 |
| 文件頁數(shù)： | 23/88頁 |
| 文件大?。?/td> | 592K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
3
Table of Contents
1
Overview ...........................................................................................................................................8
1.1
Features ..................................................................................................................................................... 8
1.1.1
Overall Features ...................................................................................................................................................8
1.1.2
PCI-X Features.....................................................................................................................................................8
1.1.3
Serial ATA Features .............................................................................................................................................8
1.2
References ................................................................................................................................................. 8
2
Electrical Characteristics ................................................................................................................9
2.1
Device Electrical Characteristics ............................................................................................................ 9
2.2
SATA Interface Timing Specifications .................................................................................................. 11
2.3
SATA Interface Transmitter Output Jitter Characteristics.................................................................. 11
2.4
CLKI SerDes Reference Clock Input Requirements ............................................................................ 12
2.5
Power Supply Noise Requirements ...................................................................................................... 12
2.6
PCI 33 MHz Timing Specifications ........................................................................................................ 12
2.7
PCI 66 MHz Timing Specifications ........................................................................................................ 13
2.8
PCI-X 133 MHz Timing Specifications................................................................................................... 13
3
Pin Definition ..................................................................................................................................14
3.1
SiI3124A Pin Listing................................................................................................................................ 14
3.2
SiI3124A Ball Mapping............................................................................................................................ 18
3.3
SiI3124A Pin Descriptions...................................................................................................................... 19
3.3.1
PCI(X) Pins.........................................................................................................................................................19
3.3.2
Flash / I
2C Pins...................................................................................................................................................20
3.3.3
Serial ATA Signals..............................................................................................................................................20
3.3.4
Test Pins ............................................................................................................................................................21
3.3.5
NC Pins ..............................................................................................................................................................21
3.3.6
Power/Ground Pins ............................................................................................................................................22
4
Package Drawing............................................................................................................................23
5
Programming Model.......................................................................................................................25
5.1
SiI3124A Block Diagram ......................................................................................................................... 25
5.2
SiI3124A S-ATA Port Block Diagram..................................................................................................... 26
5.3
Data Structures ....................................................................................................................................... 27
5.3.1
The Command Slot.............................................................................................................................................27
5.3.2
The Scatter/Gather Entry (SGE).........................................................................................................................28
5.3.3
The Scatter/Gather Table (SGT) ........................................................................................................................29
5.3.4
The Port Request Block (PRB) ...........................................................................................................................29
5.3.5
The PRB Control Field........................................................................................................................................31
5.3.6
The PRB Protocol Override Field .......................................................................................................................32
5.3.7
Standard ATA Command PRB Structure............................................................................................................33
5.3.8
PACKET Command PRB Structure....................................................................................................................35
5.3.9
Soft Reset PRB Structure...................................................................................................................................36
5.3.10
External Command PRB Structure .....................................................................................................................37
5.3.11
Interlocked Receive PRB Structure ....................................................................................................................38
5.4
Operation ................................................................................................................................................. 39
5.4.1
Command Issuance............................................................................................................................................39
5.4.2
Reset and Initialization .......................................................................................................................................39
5.4.3
Port Ready .........................................................................................................................................................40
5.4.4
Port Reset Operation..........................................................................................................................................40
5.4.5
Initialization Sequence........................................................................................................................................40
5.4.6
Interrupts and Command Completion.................................................................................................................41
5.4.7
Interrupt Sources ................................................................................................................................................41
5.4.8
Command Completion – The Slot Status Register .............................................................................................44
5.4.9
The Attention Bit .................................................................................................................................................45
5.4.10
Interrupt Service Procedure................................................................................................................................45
5.4.11
Interrupt No Clear on Read ................................................................................................................................45
5.4.12
Error Processing.................................................................................................................................................45
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