參數(shù)資料
型號： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 60/88頁
文件大?。?/td> 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
63
7.2.4
PHY Configuration
Address Offset: 48H
Access Type: Read/Write
Reset Value: 0x0000_2C05
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
PHY Config
The PHY Configuration register is reset to 0x00002C05. These bits should not be changed from their defaults as erratic
operation may result (including bits identified as Reserved).
7.2.5
BIST Control Register
Address Offset: 50H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
B
ISTenable
BISTpatsel
Reserved
B
ISTcompse
l
Reserved
BISTrun
This register is used to control Data Loopback BIST.
Bit [31]: BISTenable (R/W) – This bit enables the data paths for running data loopback BIST.
Bit [30]: BISTpatsel (R/W) – This bit selects whether a repeating pattern (supplied from the BIST
Pattern register) or a pseudorandom pattern is used for running data loopback BIST. Setting the bit
to 1 selects the repeating pattern.
Bit [29:18]: Reserved (R/W). These bits are reserved and must write zeros.
Bit [17:16]: BISTcompsel (R/W). This bit field selects the port from which loopback data is selected
for pattern comparison.
Bit [15:04]: Reserved (R/W). These bits are reserved and must write zeros.
Bit [03:00]: BISTrun (R/W). This bit field selects the port(s) that transmit loopback data.
7.2.6
BIST Pattern Register
Address Offset: 54H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
BIST Pattern
This register contains the 32-bit fixed pattern that is repeatedly transmitted in data loopback when the BISTpatsel bit (bit 30) of
the BIST Control register is set to 1.
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