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參數資料
| 型號： | SII3124ACBHU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA364 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364 |
| 文件頁數： | 65/88頁 |
| 文件大小： | 592K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
68
7.3.1
Port LRAM
Address Offset: 000H-FFFH
Access Type: Read/Write
Reset Value: indeterminate
The Port LRAM consists of 31 Slots of 128 bytes each and a 32
nd “Slot” used to hold 16 Port Multiplier Device Specific
Registers.
Address Offset
Description
000H-07FH
Slot 0
080H-0FFH
Slot 1
100H-17FH
Slot 2
180H-EFFH
Slots 3-29
F00H-F7FH
Slot 30
F80H-F83H
Port Multiplier Device 0 Status Register
F84H-F87H
Port Multiplier Device 0 QActive Register
F88H-F8BH
Port Multiplier Device 1 Status Register
F8CH-F8FH
Port Multiplier Device 1 QActive Register
F90H-FF7H
Port Multiplier Device Registers for Devices 2-14
FF8H-FFBH
Port Multiplier Device 15 Status Register
FFCH-FFFH
Port Multiplier Device 15 QActive Register
Table 7-5 Port LRAM layout
Address Offset
Description
000H-01FH
Current FIS and Control
020H-02FH
Scatter/Gather Entry 0 or ATAPI command packet
030H-03FH
Scatter/Gather Entry 1
Port Request
Block (PRB)
040H-047H
Command Activation Register (Actual)
040H-07FH
Scatter/Gather Table
1C00H-1C07H
Command Activation Register (Shadow)
Table 7-6 Port LRAM Slot layout
A Port LRAM Slot is 128 bytes used to define Serial-ATA commands. The addresses shown above are for slot 0.
7.3.2
Port Slot Status
Address Offset: 1800H
Access Type: Read
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Attention
Slot Status
This register provides the status for the 31 Command Slots for the Serial-ATA port. This register also appears along with the
Port Status register of the other 3 ports in Global register space. Reading this register will clear the Command Completion
Status for the port if the Interrupt No Clear on Read bit (bit 3) of the Port Control register is 0. The register bits are defined
below.
Bit [31]
: Attention (R) – This bit indicates that something occurred in the port that requires the attention of the host.
Other port registers must be examined to determine the origin of the error. This bit is the logical OR of the masked
interrupt conditions reported in the Port Interrupt Status register.
Bit [30:0]
: Slot Status (R) – These bits are the Active status bits corresponding to Slot numbers 30 to 0. The Active
status bit is set when a command is transferred to the Slot RAM.
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