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參數(shù)資料
| 型號： | SII3124ACBHU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA364 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364 |
| 文件頁數(shù)： | 58/88頁 |
| 文件大?。?/td> | 592K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
61
7.2.1
Port Slot Status Registers
Address Offset: 00H-0FH
Access Type: Read
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Attention
Slot Status
These 4 registers provide the Status for the 31 Command Slots for each of the 4 ports. Adjacent pairs of registers may be
accessed together as a single 64-bit access and all four registers can therefore be read in 2 bus cycles. These registers also
appear in Port register space. Reading this register will clear the Command Completion Status for the port if the Interrupt No
Clear on Read bit (bit 3) of the Port Control register is 0. The register bits are defined below.
Bit [31]
: Attention (R) – This bit indicates that something occurred in the corresponding port that requires the
attention of the host. Other port registers must be examined to determine the origin of the error. This bit is the logical
OR of the masked interrupt conditions, except for Command Completion, reported in the Port Interrupt Status
register.
Bit [30:0]
: Slot Status (R) – These bits are the Active status bits corresponding to Slot numbers 30 to 0. The Active
status bit for a slot is set when the Slot number is written to the Command Execution FIFO (direct command transfer
method) or when a Command Activation register is written (indirect command transfer method).
7.2.2
Global Control
Address Offset: 40H
Access Type: Read/Write
Reset Value: 0x8XXX_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Global
Re
set
MS
IACK
I2C
Int
Enabl
e
P
E
RR
Rpt
Ds
bl
Reserved
3Gb/s
C
a
pable
Reserved
R
E
Q64
@R
ST
D
EVSEL
@R
ST
STOP
@R
ST
TRDY
@
R
S
T
M6
6
E
N
Reserved
Port
3
Int
Enab
le
Port
2
Int
Enab
le
Port
1
Int
Enab
le
Port
0
Int
Enab
le
This register controls various functions of the chip.
Bit [31]
: Global Reset (R/W). This bit, when set to one, asserts a port reset to all ports. This bit must be cleared to
zero to allow normal operation. Once set by this bit, all port resets will remain set to one until explicitly cleared to
zero through the individual port control clear registers. Refer to the port control set register description for more
information.
Bit [30]
: MSI Acknowledge (W). Writing a one to this bit acknowledges a Message Signaled Interrupt and permits
generation of another MSI. This bit is cleared immediately after the acknowledgement is recognized by the control
logic, hence the bit will always be read as a zero.
Bit [29]
: I2C Int Enable (R/W). This bit, when set to one, allows assertion of an interrupt when the I2C Interrupt is
asserted. When set to zero, the interrupt is masked.
Bit [28]
: PERR Rpt Dsbl (R/W) – PERR Report Disable. This bit, when set to one, disables reporting of PCI bus
parity errors to the Command Execution State Machine (such errors would otherwise cause the state machine to stop
and report an error in the Command Error register).
Bit [27:25,23:20,15:4]
: Reserved (R). These bits are reserved and will return zeroes when read.
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