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參數(shù)資料
| 型號(hào)： | SII3124ACBHU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA364 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364 |
| 文件頁(yè)數(shù)： | 30/88頁(yè) |
| 文件大?。?/td> | 592K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
36
5.3.9
Soft Reset PRB Structure
To send a soft reset sequence, the host driver need only fill in the PMP field (offset 0x8, bits[11:8]) and set control_soft_reset
(control field, bit 7). The SiI3124 will send a soft reset sequence to the device and wait for a “Register – Device to Host” FIS to
deliver the device signature and terminate the command. Upon successful command completion, the host may inspect the
FIS area of the slot in SiI3124 RAM (offset 0x08 through 0x1f) to determine the returned device signature. Please note that a
soft reset is executed in the same manner as other PRBs. It will be executed in the order in which it was issued. Port Ready
(Port Status, bit 31) must be one in order to issue this command. In Table 5-8, shaded areas depict valid fields in slot RAM
following successful command completion. These fields do not need to be supplied as inputs and may be in any state upon
command issuance.
31
0
N/A
Control (0x0080)
0x00
N/A
0x04
Features / Error
Command / Status
C
R
PMP
FIS Type
0x08
Dev/Head
Cyl High
Cyl Low
Sector Number
0x0C
Features (Exp)
Cyl High (Exp)
Cyl Low (Exp)
Sector Num (Exp)
0x10
Device Control
Reserved
Sector Count (Exp)
Sector Count
0x14
N/A
0x18
N/A
0x0C
N/A
0x10
N/A
0x14
N/A
0x18
N/A
0x1C
N/A
0x20
N/A
0x24
N/A
0x28
N/A
0x2C
N/A
0x30
N/A
0x34
N/A
0x38
N/A
0x3C
Table 5-8 Port Request Block For Soft Reset Command
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