參數(shù)資料
型號： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 34/88頁
文件大?。?/td> 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
4
5.4.13
Error recovery procedures..................................................................................................................................46
6
Auto-Initialization ...........................................................................................................................48
6.1
Auto-Initialization from Flash................................................................................................................. 48
6.2
Auto-Initialization from EEPROM .......................................................................................................... 49
7
Register Definitions .......................................................................................................................50
7.1
PCI Configuration Space ........................................................................................................................ 50
7.1.1
Device ID – Vendor ID........................................................................................................................................51
7.1.2
PCI Status – PCI Command...............................................................................................................................51
7.1.3
PCI Class Code – Revision ID............................................................................................................................52
7.1.4
BIST – Header Type – Latency Timer – Cache Line Size ..................................................................................53
7.1.5
Base Address Register 0....................................................................................................................................53
7.1.6
Base Address Register 1....................................................................................................................................54
7.1.7
Base Address Register 2....................................................................................................................................54
7.1.8
Subsystem ID – Subsystem Vendor ID ..............................................................................................................55
7.1.9
Expansion ROM Base Address ..........................................................................................................................55
7.1.10
Capabilities Pointer.............................................................................................................................................56
7.1.11
Max Latency – Min Grant – Interrupt Pin – Interrupt Line ...................................................................................56
7.1.12
PCI-X Capability .................................................................................................................................................57
7.1.13
PCI-X Status.......................................................................................................................................................57
7.1.14
Header Write Enable ..........................................................................................................................................58
7.1.15
MSI Capability ....................................................................................................................................................58
7.1.16
Message Address...............................................................................................................................................58
7.1.17
MSI Message Data .............................................................................................................................................59
7.1.18
Power Management Capability...........................................................................................................................59
7.1.19
Power Management Control + Status.................................................................................................................59
7.2
Internal Register Space – Base Address 0 ........................................................................................... 60
7.2.1
Port Slot Status Registers ..................................................................................................................................61
7.2.2
Global Control ....................................................................................................................................................61
7.2.3
Global Interrupt Status........................................................................................................................................62
7.2.4
PHY Configuration..............................................................................................................................................63
7.2.5
BIST Control Register.........................................................................................................................................63
7.2.6
BIST Pattern Register.........................................................................................................................................63
7.2.7
BIST Status Register ..........................................................................................................................................64
7.2.8
Flash Address ....................................................................................................................................................64
7.2.9
Flash Memory Data / GPIO Control....................................................................................................................65
7.2.10
I
2C Address ........................................................................................................................................................65
7.2.11
I
2C Data / Control ...............................................................................................................................................66
7.3
Internal Register Space – Base Address 1 ........................................................................................... 67
7.3.1
Port LRAM..........................................................................................................................................................68
7.3.2
Port Slot Status ..................................................................................................................................................68
7.3.3
Port Control Set ..................................................................................................................................................69
7.3.4
Port Status..........................................................................................................................................................70
7.3.5
Port Control Clear...............................................................................................................................................70
7.3.6
Port Interrupt Status ...........................................................................................................................................70
7.3.7
Port Interrupt Enable Set / Port Interrupt Enable Clear.......................................................................................72
7.3.8
32-bit Activation Upper Address .........................................................................................................................72
7.3.9
Port Command Execution FIFO .........................................................................................................................72
7.3.10
Port Command Error ..........................................................................................................................................73
7.3.11
Port FIS Configuration ........................................................................................................................................75
7.3.12
Port PCI(X) Request FIFO Threshold.................................................................................................................76
7.3.13
Port 8B/10B Decode Error Counter ....................................................................................................................76
7.3.14
Port CRC Error Counter .....................................................................................................................................77
7.3.15
Port Handshake Error Counter ...........................................................................................................................77
7.3.16
Port PHY Configuration ......................................................................................................................................78
7.3.17
Port Device Status Register ...............................................................................................................................78
7.3.18
Port Device QActive Register .............................................................................................................................79
7.3.19
Port Context Register .........................................................................................................................................79
7.3.20
SControl .............................................................................................................................................................80
7.3.21
SStatus...............................................................................................................................................................81
7.3.22
SError .................................................................................................................................................................82
7.3.23
SActive ...............................................................................................................................................................82
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