參數(shù)資料
型號(hào)： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 11/88頁
文件大?。?/td> 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
19
3.3 SiI3124 Pin Descriptions
3.3.1
PCI(X) Pins
Signal Name
Pin Number(s)
Description
PCI_AD[63:0]
K20, K17, K19, J19,
J20, J17, H20, H17,
H19, G19, G20,
G17, F20, F17, F19,
E19, E20, E17, D20,
D19, C20, C19, B20,
D17, A19, B18, A18,
B17, A17, B16, A16,
D16, Y8, U8, W8,
W9, Y9, U9, Y10,
U10, Y11, U11, Y12,
U12, W12, W13,
Y13, U13, U17, Y18,
W18, V20, V19,
U20, U19, T19, R20,
R17, R19, P19, P20,
P17, N20, N17
Address/Attribute/Data. PCI_AD[63:0] is the multiplexed
address/attribute/data bus. Each bus transaction consists of an address phase
followed by an attribute phase (PCI-X only), then one ore more data phases.
PCI_CBEN[7:0]
M19, M20, L19, L20,
W10, Y14, Y17, T17
Command/Byte Enable. PCI_CBEN is the multiplexed command/byte-enable
bus. During the address phase this bus carries the command. During the
attribute phase (PCI-X only) PCI_CBEN[3:0] carries the upper 4 bits of the byte
count. During the data phase this bus carries byte enables.
PCI_IDSEL
W11
Initialization Device Select. This is the chip select for configuration read/write
operations.
PCI_FRAME_N
U14
Frame. PCI_FRAME_N is asserted to indicate the beginning of a bus
operation. It is deasserted when the transaction is in the final data phase or
has completed.
PCI_IRDY_N
W14
Initiator Ready. PCI_IRDY_N is asserted by a bus master to indicate that it
can complete a data transaction.
PCI_TRDY_N
U16
Target Ready. PCI_TRDY_N is asserted by a target to indicate that it can
complete the current data transaction.
PCI_DEVSEL_N
W15
Device Select. PCI_DEVSEL_N is asserted to indicate that the target has
decoded its own address or a Split Completion cycle (PCI-X only).
PCI_STOP_N
U15
Stop. PCI_STOP_N indicates the current target is requesting that the master
stop the current transaction.
PCI_LOCK_N
Y15
Lock. PCI_LOCK_N indicates that the current transaction on the PCI bus
needs to be a Locked transaction.
PCI_REQ_N
Y7
Request. PCI_REQ_N indicates to the system arbiter that the SiI3124 wants to
gain control of the PCI bus to perform a transaction.
PCI_GNT_N
U7
Grant. PCI_GNT_N indicates that the SiI3124 has been given control of the
bus to perform a transaction.
PCI_REQ64_N
M17
Request64. PCI_REQ64_N is asserted by a bus master to request a 64-bit
transaction.
PCI_ACK64_N
N19
Acknowledge64. PCI_ACK64_N is asserted by a target to acknowledge that a
64-bit transaction is accepted.
PCI_PAR
W17
Parity. PCI_PAR carries even parity covering the PCI_AD[31:0] and
PCI_CBEN[3:0] buses.
PCI_PAR64
L17
Parity. PCI_PAR64 carries even parity covering the PCI_AD[63:32] and
PCI_CBEN[7:4] buses.
PCI_PERR_N
W16
Parity Error. PCI_PERR_N indicates the detection of a data parity error.
PCI_SERR_N
Y16
System Error. PCI_SERR_N indicates detection of an address or attribute
parity error or of any other system error where the result will be catastrophic.
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