參數(shù)資料
型號(hào)： SII3124ACBHU
元件分類(lèi)： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁(yè)數(shù)： 68/88頁(yè)
文件大小： 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
70
one. This bit is set to one by the Global reset, which is set by a PCI reset, and remains set until cleared by the
host (by writing a one to bit 0 of the Port Control Clear register).
The register bits that are not initialized by the Port Reset are:
OOB Bypass (bit 25) in Port Control (this register)
Port PHY Configuration register (all bits)
7.3.4
Port Status
Address Offset: 1000H
Access Type: Read
Reset Value: 0x001F_0001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Port
R
eady
Reserved
OOB
Bypas
s
Reserved
Active Slot
LED
On
Auto
I
n
te
rl
oc
k
Acc
e
p
t
PM
Enable
Int
e
rlock
A
c
cept
Int
e
rlock
R
e
je
ct
3
2
-bi
tAc
ti
v
a
ti
on
Scrambl
e
Dis
a
ble
CONT
Dis
a
ble
Transmit
BIST
Re
s
u
me
Pac
ket
Length
LE
D
Dis
a
b
le
Inte
rrupt
NCoR
Port
Init
ializ
e
D
evic
e
R
e
s
e
t
Port
R
e
set
This register is used to determine the status of various port functions.
Bit [31]
: Port Ready (R). This bit reports the Port Ready status. The transition from 0 to 1 of this bit generates
the Port Ready Interrupt Status (bit 18/2 of the Port Interrupt Status register).
Bit [30:26,24:21]
: Reserved (R). These bits are reserved.
Bit [20:16]
: Active Slot (R). This bit field contains the slot number of the command currently being executed.
When a command error occurs, this bit field indicates the slot containing the command in error.
Bit [25,15:0]
: These bits reflect the current state of the corresponding bits in the Port Control register. Refer to
the Port Control Set register for a complete description.
7.3.5
Port Control Clear
Address Offset: 1004H
Access Type: Write One To Clear
Reset Value: N/A
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
OOB
Bypas
s
Reserved
LED
On
A
u
to
Int
e
rlock
A
c
cep
t
PM
Enable
R
eser
ved
32-
bit
A
c
ti
vat
ion
Scrambl
e
Dis
a
ble
CONT
Dis
a
ble
Transmit
B
IST
R
eser
ved
Pac
ket
Length
LE
D
Dis
a
b
le
Inte
rrupt
NCoR
R
eser
ved
Port
R
eset
This register is used to direct various port operations. A one written to a bit position clears that bit in the control register.
Bit [31:26,24:16,12:11,6,2:1]
: Reserved (R). These bits are reserved.
Bit [25,15:13,10:7,5:3,0]
: (W1C) Writing a one to these bits clears the associated bit position of the Port Control
register. Refer to the Port Control Set register for bit descriptions.
7.3.6
Port Interrupt Status
Address Offset: 1008H
Access Type: Read/Write 1 Clear
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
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