參數(shù)資料
型號： SII3124ACBHU
元件分類： 總線控制器
英文描述： PCI BUS CONTROLLER, PBGA364
封裝： 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364
文件頁數(shù)： 55/88頁
文件大小： 592K
代理商： SII3124ACBHU
PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
59
7.1.17 MSI Message Data
Address Offset: 60H
Access Type: Read/Write
Reset Value: 0x0000_0000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
Reserved
Message Data
This register specifies the MSI Message Data. The register bits are defined below.
Bit [31:16]
: Reserved (R) – This bit field is reserved and returns zeros on a read.
Bit [15:00]
:
Message Data (R/W) – This bit field specifies the Message Data for an MSI memory write
transaction.
7.1.18 Power Management Capability
Address Offset: 64H
Access Type: Read Only
Reset Value: 0x0622_4001
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PME Support
PPM
D2
Support
PPM
D1
Support
Auxiliary
Current
Dev
Spe
c
ia
lInit
R
eser
ved
PM
E
C
lock
PPM Rev
Next Capability Pointer
Capability ID
This register defines the power management capabilities associated with the PCI bus. The register bits are defined below.
Bit [31:27]
: PME Support (R) – Power Management Event Support. This bit field is hardwired to 00H; the
SiI3124 does not support PME.
Bit [26]
: PPM D2 Support (R) – PCI Power Management D2 Support. This bit is hardwired to 1.
Bit [25]
: PPM D1 Support (R) – PCI Power Management D1 Support. This bit is hardwired to 1.
Bit [24:22]
: Auxiliary Current (R) – Auxiliary Current. This bit field is hardwired to 000B.
Bit [21]
: Dev Special Init (R) – Device Special Initialization. This bit is hardwired to 1 to indicate that the SiI3124
requires special initialization.
Bit [20]
: Reserved (R). This bit is reserved and returns zero on a read.
Bit [19]
: PME Clock (R) – Power Management Event Clock. This bit is hardwired to 0; the SiI3124 does not
support PME.
Bit [18:16]
: PPM Rev (R) – PCI Power Management Revision. This bit field is hardwired to 010B to indicate
compliance with the PCI Power Management Interface Specification revision 1.1.
Bit [15:08]
: Next Capability Pointer (R) – PCI Next Capability Pointer. This bit field is hardwired to 40H to point
to the 2
nd Capabilities register, the PCI-X Capability.
Bit [07:00]
: Capability ID (R) – PCI Capability ID. This bit field is hardwired to 01H to indicate that this is a PCI
Power Management Capability.
7.1.19 Power Management Control + Status
Address Offset: 68H
Access Type: Read/Write
Reset Value: 0x1900_2000
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 09 08 07 06 05 04 03 02 01 00
PPM Data
Reserved
PM
E
St
at
us
PPM
D
a
ta
S
cal
e
PPM Data Sel
PM
E
Ena
Reserved
PPM
Power
St
at
e
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