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參數(shù)資料
| 型號： | SII3124ACBHU |
| 元件分類： | 總線控制器 |
| 英文描述： | PCI BUS CONTROLLER, PBGA364 |
| 封裝： | 21 X 21 MM, 1 MM PITCH, GREEN, BGA-364 |
| 文件頁數(shù)： | 19/88頁 |
| 文件大小： | 592K |
| 代理商： | SII3124ACBHU |
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PCI-X to Serial ATA Controller
Data Sheet
Silicon Image, Inc.
2006 Silicon Image, Inc.
SiI-DS-0160-C
26
5.2 SiI3124 S-ATA Port Block Diagram
The block diagram below shows the logic structure of each of the four SiI3124 Serial-ATA Ports.
Data Path B
Local PCI-X Arbiter
PCI-X – LRAM
DMA Controller
Data Path A
2 Addresses
PCI-X – SATA
DMA Controller
Data Path B
1 Address
Command Fetch
Machine
Command
Fetch FIFO
31 x 5
Command
Execution
Machine
Command
Execute FIFO
31 x 5
Command
Receive FIFO
31 x 5
PCI-X Application
Interface
Initiator
PCI-X / SATA
Data FIFO
256 x 64
SATA
Enhanced
Link
Rx FIFO
Registers
SATA PHY
Port Register File
Data Path A
LRAM
512 x 64
Dual Port
P
o
r
t
B
P
o
r
t
A
Figure 5-2 Port Logic Block Diagram
The Port Logic consists of:
A Local PCI-X Arbiter that arbitrates between the two DMA Controllers
A DMA Controller for the PCI-X to LRAM Data Path
A DMA Controller for the PCI-X to Serial-ATA Data Path
A 512x64 Local RAM (LRAM) that contains: 31 LRAM Slots each of which is 128 bytes (16 Qwords ) and 128 bytes
used to support 16 Port Multiplier devices (1 Qword per device)
A Data FIFO that contains 2048 bytes (256 Qwords)
A State Machine for Command Fetch
A State Machine for Command Execution
A Serial-ATA Link
A Serial-ATA PHY
Each of the two state machines has an associated FIFO which, when non-empty, indicates that processing is required. The
FIFO is loaded with a 5-bit command “slot” number to activate a state machine. The slot number can range from 0 to 30,
corresponding to the maximum number of active commands supported.
Command flow begins with a host driver building a command in a non-cached region of host memory. The data structure is
referred to as a PRB (Port Request Block). The 64-byte PRB is transferred into an available command slot in the LRAM by
one of two methods: the direct method or the indirect method. The host driver is responsible for determining which slots are
available. Either of the two command transfer methods may be used for each command transfer. The two methods are:
Direct Command Transfer Method – Host controlled write to Slot
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